1# 2# Copyright (c) 2023-2024, Linaro Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include lib/libfdt/libfdt.mk 8include common/fdt_wrappers.mk 9 10PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ 11 -I${PLAT_QEMU_COMMON_PATH}/ \ 12 -I${PLAT_QEMU_COMMON_PATH}/include \ 13 -I${PLAT_QEMU_PATH}/include \ 14 -Iinclude/common/tbbr 15 16ifeq (${ARCH},aarch32) 17QEMU_CPU_LIBS := lib/cpus/${ARCH}/cortex_a15.S 18else 19QEMU_CPU_LIBS := lib/cpus/aarch64/aem_generic.S \ 20 lib/cpus/aarch64/cortex_a53.S \ 21 lib/cpus/aarch64/cortex_a55.S \ 22 lib/cpus/aarch64/cortex_a57.S \ 23 lib/cpus/aarch64/cortex_a72.S \ 24 lib/cpus/aarch64/cortex_a76.S \ 25 lib/cpus/aarch64/cortex_a710.S \ 26 lib/cpus/aarch64/neoverse_n1.S \ 27 lib/cpus/aarch64/neoverse_v1.S \ 28 lib/cpus/aarch64/neoverse_n2.S \ 29 lib/cpus/aarch64/qemu_max.S 30 31PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH} 32endif 33 34PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \ 35 ${PLAT_QEMU_COMMON_PATH}/qemu_console.c \ 36 drivers/arm/pl011/${ARCH}/pl011_console.S 37 38include lib/xlat_tables_v2/xlat_tables.mk 39PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} 40 41ifneq ($(ENABLE_STACK_PROTECTOR), 0) 42 PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c 43endif 44 45BL1_SOURCES += drivers/io/io_semihosting.c \ 46 drivers/io/io_storage.c \ 47 drivers/io/io_fip.c \ 48 drivers/io/io_memmap.c \ 49 lib/semihosting/semihosting.c \ 50 lib/semihosting/${ARCH}/semihosting_call.S \ 51 ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \ 52 ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \ 53 ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c \ 54 ${QEMU_CPU_LIBS} 55 56BL2_SOURCES += drivers/io/io_semihosting.c \ 57 drivers/io/io_storage.c \ 58 drivers/io/io_fip.c \ 59 drivers/io/io_memmap.c \ 60 lib/semihosting/semihosting.c \ 61 lib/semihosting/${ARCH}/semihosting_call.S \ 62 ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \ 63 ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \ 64 ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c \ 65 ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c \ 66 ${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \ 67 common/desc_image_load.c \ 68 common/fdt_fixup.c \ 69 ${FDT_WRAPPERS_SOURCES} 70 71BL31_SOURCES += ${QEMU_CPU_LIBS} \ 72 lib/semihosting/semihosting.c \ 73 lib/semihosting/${ARCH}/semihosting_call.S \ 74 plat/common/plat_psci_common.c \ 75 ${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \ 76 ${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \ 77 common/fdt_fixup.c \ 78 ${QEMU_GIC_SOURCES} 79 80# CPU flag enablement 81ifeq (${ARCH},aarch64) 82 83# Cpu core architecture level: 84# v8.0: a53, a57, a72 85# v8.2: a55, a76, n1 86# v8.4: v1 87# v9.0: a710, n2 88# 89# 90# We go v8.0 by default and will enable all features we want 91 92ARM_ARCH_MAJOR ?= 8 93ARM_ARCH_MINOR ?= 0 94 95# 8.0 96ENABLE_FEAT_CSV2_2 := 2 97 98# 8.1 99ENABLE_FEAT_PAN := 2 100ENABLE_FEAT_VHE := 2 101 102# 8.2 103# TF-A currently does not permit dynamic detection of FEAT_RAS 104# so this is the only safe setting 105ENABLE_FEAT_RAS := 0 106 107# 8.4 108ENABLE_FEAT_SEL2 := 2 109ENABLE_FEAT_DIT := 2 110ENABLE_TRF_FOR_NS := 2 111 112# 8.5 113ENABLE_FEAT_RNG := 2 114# TF-A currently does not do dynamic detection of FEAT_SB. 115# Compiler puts SB instruction when it is enabled. 116ENABLE_FEAT_SB := 0 117 118# 8.6 119ENABLE_FEAT_ECV := 2 120ENABLE_FEAT_FGT := 2 121 122# 8.7 123ENABLE_FEAT_HCX := 2 124 125# 8.8 126ENABLE_FEAT_TCR2 := 2 127ENABLE_FEAT_SCTLR2 := 2 128ENABLE_FEAT_S2PIE := 2 129ENABLE_FEAT_S1PIE := 2 130ENABLE_FEAT_S2POE := 2 131ENABLE_FEAT_S1POE := 2 132 133# 9.3 134ENABLE_FEAT_GCS := 2 135 136# SPM_MM is not compatible with ENABLE_SVE_FOR_NS (build breaks) 137ifeq (${SPM_MM},1) 138 ENABLE_SVE_FOR_NS := 0 139 ENABLE_SME_FOR_NS := 0 140else 141 ENABLE_SVE_FOR_NS := 2 142 ENABLE_SME_FOR_NS := 2 143endif 144 145ifeq (${ENABLE_RME},1) 146BL31_SOURCES += plat/qemu/common/qemu_plat_attest_token.c \ 147 plat/qemu/common/qemu_realm_attest_key.c 148endif 149 150# Treating this as a memory-constrained port for now 151USE_COHERENT_MEM := 0 152 153# This can be overridden depending on CPU(s) used in the QEMU image 154HW_ASSISTED_COHERENCY := 1 155 156CTX_INCLUDE_AARCH32_REGS := 0 157ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1) 158$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled") 159endif 160 161# Pointer Authentication sources 162ifeq ($(BRANCH_PROTECTION),$(filter $(BRANCH_PROTECTION),1 2 3 5)) 163PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c 164endif 165 166ifeq (${TRANSFER_LIST}, 1) 167include lib/transfer_list/transfer_list.mk 168endif 169 170ifeq (${HOB_LIST}, 1) 171include lib/hob/hob.mk 172endif 173 174endif 175