| #
b1e50695 |
| 18-Dec-2025 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "fix(layerscape): unlock write access SMMU_CBn_ACTLR" into integration
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| #
40400197 |
| 21-May-2025 |
Alexander Stein <alexander.stein@ew.tq-group.com> |
fix(layerscape): unlock write access SMMU_CBn_ACTLR
This patch is to fix Errata #841119 and #826419 (see [1]) failed
apply in Linux because of SMMU_CBn_ACTLR register can't be modified
in non-secure
fix(layerscape): unlock write access SMMU_CBn_ACTLR
This patch is to fix Errata #841119 and #826419 (see [1]) failed
apply in Linux because of SMMU_CBn_ACTLR register can't be modified
in non-secure states. This mimics the changes from commit 0ca1d8fba
("fix(layerscape): unlock write access SMMU_CBn_ACTLR")
[1] https://developer.arm.com/documentation/epm133458/latest
Change-Id: I3f1e35150f66c604be2e10b3f91b39b2a7dc62bd
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
show more ...
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| #
c99e3b74 |
| 14-Oct-2025 |
Yann Gautier <yann.gautier@st.com> |
Merge "fix(nxp): tbbr: adds snvs_init" into integration
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| #
ce9b87e7 |
| 13-May-2025 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
fix(nxp): tbbr: adds snvs_init
Fix to initialize the SNVS driver as part of soc early init, that sets
the snvs base address to read or write to the memory mapped registers of
SNVS IP.
Change-Id: I6
fix(nxp): tbbr: adds snvs_init
Fix to initialize the SNVS driver as part of soc early init, that sets
the snvs base address to read or write to the memory mapped registers of
SNVS IP.
Change-Id: I6ebd1d17302647487ec786f5e20f51450ce29473
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
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| #
dca5ce11 |
| 26-Jan-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "refactor(ls1028a): fix header file group issue" into integration
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| #
40886d5a |
| 20-Jan-2022 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
refactor(ls1028a): fix header file group issue
ocram.h should be in platform includes group.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I43b6a279e48e1a173f8e7c601f2c8d48e6efc647
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| #
381d6850 |
| 18-Oct-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes Id7d4f5df,If82542cc,I0ba80057,I75a443db,Ifa18b4fc, ... into integration
* changes:
feat(nxp/common/ocram): add driver for OCRAM initialization
feat(plat/nxp/common): add EESR regis
Merge changes Id7d4f5df,If82542cc,I0ba80057,I75a443db,Ifa18b4fc, ... into integration
* changes:
feat(nxp/common/ocram): add driver for OCRAM initialization
feat(plat/nxp/common): add EESR register definition
fix(plat/nxp/ls1028a): fix compile error when enable fuse provision
fix(drivers/nxp/sfp): fix compile warning
fix(plat/nxp/ls1028a): define endianness of scfg and gpio
fix(nxp/scfg): fix endianness checking
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| #
a0da9c4b |
| 27-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
fix(plat/nxp/ls1028a): fix compile error when enable fuse provision
Fix the error that no "gpio_init_data" is defined when
build with "FUSE_PROG=1".
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
C
fix(plat/nxp/ls1028a): fix compile error when enable fuse provision
Fix the error that no "gpio_init_data" is defined when
build with "FUSE_PROG=1".
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I0ba8005725fe33c6d8e68b4d52539f5d5d749f1a
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| #
ab5964aa |
| 26-Sep-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes I9c7cc586,I48ee254a,I9f65c6af,I5872d95b,I2dbbdcb4, ... into integration
* changes:
feat(docs/nxp/layerscape): add ls1028a soc and board support
feat(plat/nxp/ls1028ardb): add ls102
Merge changes I9c7cc586,I48ee254a,I9f65c6af,I5872d95b,I2dbbdcb4, ... into integration
* changes:
feat(docs/nxp/layerscape): add ls1028a soc and board support
feat(plat/nxp/ls1028ardb): add ls1028ardb board support
feat(plat/nxp/ls1028a): add ls1028a soc support
feat(plat/nxp/common): define default SD buffer
feat(driver/nxp/xspi): add MT35XU02G flash info
feat(plat/nxp/common): add SecMon register definition for ch_3_2
feat(driver/nxp/dcfg): define RSTCR_RESET_REQ
feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS
feat(plat/nxp/common): define default PSCI features if not defined
feat(plat/nxp/common): define common macro for ARM registers
feat(plat/nxp/common): add CCI and EPU address definition
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| #
9d250f03 |
| 10-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(plat/nxp/ls1028a): add ls1028a soc support
The QorIQ LS1028A processor integrates two 64-bit ARM Cortex-A72
cores with a GPU and LCD controller, as well as a TSNenabled
Ethernet port and a TSN-
feat(plat/nxp/ls1028a): add ls1028a soc support
The QorIQ LS1028A processor integrates two 64-bit ARM Cortex-A72
cores with a GPU and LCD controller, as well as a TSNenabled
Ethernet port and a TSN-enabled switch with four external ports.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Change-Id: I9f65c6af5db7e20702828cd208290c1b43a54941
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