1 /*
2 * Copyright 2018-2021, 2025 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <endian.h>
8
9 #include <arch.h>
10 #include <caam.h>
11 #include <cassert.h>
12 #include <cci.h>
13 #include <common/debug.h>
14 #include <dcfg.h>
15 #include <i2c.h>
16 #include <lib/xlat_tables/xlat_tables_v2.h>
17 #include <ls_interconnect.h>
18 #include <mmio.h>
19 #ifdef POLICY_FUSE_PROVISION
20 #include <nxp_gpio.h>
21 #endif
22 #if TRUSTED_BOARD_BOOT
23 #include <nxp_smmu.h>
24 #endif
25 #include <nxp_timer.h>
26 #include <plat_console.h>
27 #include <plat_gic.h>
28 #include <plat_tzc400.h>
29 #include <pmu.h>
30 #include <scfg.h>
31 #if defined(NXP_SFP_ENABLED)
32 #include <sfp.h>
33 #endif
34 #if TRUSTED_BOARD_BOOT
35 #include <snvs.h>
36 #endif
37
38 #include <errata.h>
39 #ifdef CONFIG_OCRAM_ECC_EN
40 #include <ocram.h>
41 #endif
42 #include "plat_common.h"
43 #include "platform_def.h"
44 #include "soc.h"
45
46 static dcfg_init_info_t dcfg_init_data = {
47 .g_nxp_dcfg_addr = NXP_DCFG_ADDR,
48 .nxp_sysclk_freq = NXP_SYSCLK_FREQ,
49 .nxp_ddrclk_freq = NXP_DDRCLK_FREQ,
50 .nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER,
51 };
52
53 static struct soc_type soc_list[] = {
54 SOC_ENTRY(LS1017AN, LS1017AN, 1, 1),
55 SOC_ENTRY(LS1017AE, LS1017AE, 1, 1),
56 SOC_ENTRY(LS1018AN, LS1018AN, 1, 1),
57 SOC_ENTRY(LS1018AE, LS1018AE, 1, 1),
58 SOC_ENTRY(LS1027AN, LS1027AN, 1, 2),
59 SOC_ENTRY(LS1027AE, LS1027AE, 1, 2),
60 SOC_ENTRY(LS1028AN, LS1028AN, 1, 2),
61 SOC_ENTRY(LS1028AE, LS1028AE, 1, 2),
62 };
63
64 CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256,
65 assert_invalid_ls1028a_cluster_count);
66
67 /*
68 * Function returns the base counter frequency
69 * after reading the first entry at CNTFID0 (0x20 offset).
70 *
71 * Function is used by:
72 * 1. ARM common code for PSCI management.
73 * 2. ARM Generic Timer init.
74 *
75 */
plat_get_syscnt_freq2(void)76 unsigned int plat_get_syscnt_freq2(void)
77 {
78 unsigned int counter_base_frequency;
79 /*
80 * Below register specifies the base frequency of the system counter.
81 * As per NXP Board Manuals:
82 * The system counter always works with SYS_REF_CLK/4 frequency clock.
83 */
84 counter_base_frequency = mmio_read_32(NXP_TIMER_ADDR + CNTFID_OFF);
85
86 return counter_base_frequency;
87 }
88
89 #ifdef IMAGE_BL2
90
91 #ifdef POLICY_FUSE_PROVISION
92 static gpio_init_info_t gpio_init_data = {
93 .gpio1_base_addr = NXP_GPIO1_ADDR,
94 .gpio2_base_addr = NXP_GPIO2_ADDR,
95 .gpio3_base_addr = NXP_GPIO3_ADDR,
96 };
97 #endif
98
soc_preload_setup(void)99 void soc_preload_setup(void)
100 {
101 }
102
soc_early_init(void)103 void soc_early_init(void)
104 {
105 uint8_t num_clusters, cores_per_cluster;
106
107 #if TRUSTED_BOARD_BOOT
108 snvs_init(NXP_SNVS_ADDR);
109 #endif
110
111 #ifdef CONFIG_OCRAM_ECC_EN
112 ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE);
113 #endif
114 dcfg_init(&dcfg_init_data);
115 enable_timer_base_to_cluster(NXP_PMU_ADDR);
116 enable_core_tb(NXP_PMU_ADDR);
117 dram_regions_info_t *dram_regions_info = get_dram_regions_info();
118
119 #ifdef POLICY_FUSE_PROVISION
120 gpio_init(&gpio_init_data);
121 sec_init(NXP_CAAM_ADDR);
122 #endif
123
124 #if LOG_LEVEL > 0
125 /* Initialize the console to provide early debug support */
126 plat_console_init(NXP_CONSOLE_ADDR,
127 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
128 #endif
129 enum boot_device dev = get_boot_dev();
130 /*
131 * Mark the buffer for SD in OCRAM as non secure.
132 * The buffer is assumed to be at end of OCRAM for
133 * the logic below to calculate TZPC programming
134 */
135 if (dev == BOOT_DEVICE_EMMC || dev == BOOT_DEVICE_SDHC2_EMMC) {
136 /*
137 * Calculate the region in OCRAM which is secure
138 * The buffer for SD needs to be marked non-secure
139 * to allow SD to do DMA operations on it
140 */
141 uint32_t secure_region = (NXP_OCRAM_SIZE - NXP_SD_BLOCK_BUF_SIZE);
142 uint32_t mask = secure_region/TZPC_BLOCK_SIZE;
143
144 mmio_write_32(NXP_OCRAM_TZPC_ADDR, mask);
145
146 /* Add the entry for buffer in MMU Table */
147 mmap_add_region(NXP_SD_BLOCK_BUF_ADDR, NXP_SD_BLOCK_BUF_ADDR,
148 NXP_SD_BLOCK_BUF_SIZE, MT_DEVICE | MT_RW | MT_NS);
149 }
150
151 #if TRUSTED_BOARD_BOOT
152 uint32_t mode;
153
154 sfp_init(NXP_SFP_ADDR);
155
156 /*
157 * For secure boot disable SMMU.
158 * Later when platform security policy comes in picture,
159 * this might get modified based on the policy
160 */
161 if (check_boot_mode_secure(&mode) == true) {
162 bypass_smmu(NXP_SMMU_ADDR);
163 }
164
165 /*
166 * For Mbedtls currently crypto is not supported via CAAM
167 * enable it when that support is there. In tbbr.mk
168 * the CAAM_INTEG is set as 0.
169 */
170 #ifndef MBEDTLS_X509
171 /* Initialize the crypto accelerator if enabled */
172 if (is_sec_enabled()) {
173 sec_init(NXP_CAAM_ADDR);
174 } else {
175 INFO("SEC is disabled.\n");
176 }
177 #endif
178 #endif
179
180 /* Set eDDRTQ for DDR performance */
181 scfg_setbits32((void *)(NXP_SCFG_ADDR + 0x210), 0x1f1f1f1f);
182
183 soc_errata();
184
185 /*
186 * Initialize Interconnect for this cluster during cold boot.
187 * No need for locks as no other CPU is active.
188 */
189 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
190
191 /*
192 * Enable Interconnect coherency for the primary CPU's cluster.
193 */
194 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
195 plat_ls_interconnect_enter_coherency(num_clusters);
196
197 delay_timer_init(NXP_TIMER_ADDR);
198 i2c_init(NXP_I2C_ADDR);
199 dram_regions_info->total_dram_size = init_ddr();
200 }
201
soc_bl2_prepare_exit(void)202 void soc_bl2_prepare_exit(void)
203 {
204 #if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE)
205 set_sfp_wr_disable();
206 #endif
207 }
208
209 /*
210 * This function returns the boot device based on RCW_SRC
211 */
get_boot_dev(void)212 enum boot_device get_boot_dev(void)
213 {
214 enum boot_device src = BOOT_DEVICE_NONE;
215 uint32_t porsr1;
216 uint32_t rcw_src;
217
218 porsr1 = read_reg_porsr1();
219
220 rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT;
221 switch (rcw_src) {
222 case FLEXSPI_NOR:
223 src = BOOT_DEVICE_FLEXSPI_NOR;
224 INFO("RCW BOOT SRC is FLEXSPI NOR\n");
225 break;
226 case FLEXSPI_NAND2K_VAL:
227 case FLEXSPI_NAND4K_VAL:
228 INFO("RCW BOOT SRC is FLEXSPI NAND\n");
229 src = BOOT_DEVICE_FLEXSPI_NAND;
230 break;
231 case SDHC1_VAL:
232 src = BOOT_DEVICE_EMMC;
233 INFO("RCW BOOT SRC is SD\n");
234 break;
235 case SDHC2_VAL:
236 src = BOOT_DEVICE_SDHC2_EMMC;
237 INFO("RCW BOOT SRC is EMMC\n");
238 break;
239 default:
240 break;
241 }
242
243 return src;
244 }
245
246 /*
247 * This function sets up access permissions on memory regions
248 ****************************************************************************/
soc_mem_access(void)249 void soc_mem_access(void)
250 {
251 dram_regions_info_t *info_dram_regions = get_dram_regions_info();
252 struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION];
253 int dram_idx = 0;
254 /* index 0 is reserved for region-0 */
255 int index = 1;
256
257 for (dram_idx = 0; dram_idx < info_dram_regions->num_dram_regions;
258 dram_idx++) {
259 if (info_dram_regions->region[dram_idx].size == 0) {
260 ERROR("DDR init failure, or");
261 ERROR("DRAM regions not populated correctly.\n");
262 break;
263 }
264
265 index = populate_tzc400_reg_list(tzc400_reg_list,
266 dram_idx, index,
267 info_dram_regions->region[dram_idx].addr,
268 info_dram_regions->region[dram_idx].size,
269 NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE);
270 }
271
272 mem_access_setup(NXP_TZC_ADDR, index, tzc400_reg_list);
273 }
274
275 #else
276
277 static unsigned char _power_domain_tree_desc[NUMBER_OF_CLUSTERS + 2];
278 /*
279 * This function dynamically constructs the topology according to
280 * SoC Flavor and returns it.
281 */
plat_get_power_domain_tree_desc(void)282 const unsigned char *plat_get_power_domain_tree_desc(void)
283 {
284 uint8_t num_clusters, cores_per_cluster;
285 unsigned int i;
286
287 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
288 /*
289 * The highest level is the system level. The next level is constituted
290 * by clusters and then cores in clusters.
291 */
292 _power_domain_tree_desc[0] = 1;
293 _power_domain_tree_desc[1] = num_clusters;
294
295 for (i = 0; i < _power_domain_tree_desc[1]; i++)
296 _power_domain_tree_desc[i + 2] = cores_per_cluster;
297
298 return _power_domain_tree_desc;
299 }
300
301 /*
302 * This function returns the core count within the cluster corresponding to
303 * `mpidr`.
304 */
plat_ls_get_cluster_core_count(u_register_t mpidr)305 unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr)
306 {
307 uint8_t num_clusters, cores_per_cluster;
308
309 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
310 return num_clusters;
311 }
312
soc_early_platform_setup2(void)313 void soc_early_platform_setup2(void)
314 {
315 dcfg_init(&dcfg_init_data);
316 /* Initialize system level generic timer for Socs */
317 delay_timer_init(NXP_TIMER_ADDR);
318
319 #if LOG_LEVEL > 0
320 /* Initialize the console to provide early debug support */
321 plat_console_init(NXP_CONSOLE_ADDR,
322 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
323 #endif
324 }
325
soc_platform_setup(void)326 void soc_platform_setup(void)
327 {
328 /* Initialize the GIC driver, cpu and distributor interfaces */
329 static uintptr_t target_mask_array[PLATFORM_CORE_COUNT];
330 static interrupt_prop_t ls_interrupt_props[] = {
331 PLAT_LS_G1S_IRQ_PROPS(INTR_GROUP1S),
332 PLAT_LS_G0_IRQ_PROPS(INTR_GROUP0)
333 };
334
335 plat_ls_gic_driver_init(NXP_GICD_ADDR, NXP_GICR_ADDR,
336 PLATFORM_CORE_COUNT,
337 ls_interrupt_props,
338 ARRAY_SIZE(ls_interrupt_props),
339 target_mask_array,
340 plat_core_pos);
341
342 plat_ls_gic_init();
343 enable_init_timer();
344 }
345
346 /* This function initializes the soc from the BL31 module */
soc_init(void)347 void soc_init(void)
348 {
349 uint8_t num_clusters, cores_per_cluster;
350
351 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
352
353 /* Low-level init of the soc */
354 soc_init_lowlevel();
355 _init_global_data();
356 soc_init_percpu();
357 _initialize_psci();
358
359 /*
360 * Initialize Interconnect for this cluster during cold boot.
361 * No need for locks as no other CPU is active.
362 */
363 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
364
365 /* Enable Interconnect coherency for the primary CPU's cluster. */
366 plat_ls_interconnect_enter_coherency(num_clusters);
367
368 /* Set platform security policies */
369 _set_platform_security();
370
371 /* Init SEC Engine which will be used by SiP */
372 if (is_sec_enabled()) {
373 sec_init(NXP_CAAM_ADDR);
374 } else {
375 INFO("SEC is disabled.\n");
376 }
377 }
378
379 #ifdef NXP_WDOG_RESTART
wdog_interrupt_handler(uint32_t id,uint32_t flags,void * handle,void * cookie)380 static uint64_t wdog_interrupt_handler(uint32_t id, uint32_t flags,
381 void *handle, void *cookie)
382 {
383 uint8_t data = WDOG_RESET_FLAG;
384
385 wr_nv_app_data(WDT_RESET_FLAG_OFFSET,
386 (uint8_t *)&data, sizeof(data));
387
388 mmio_write_32(NXP_RST_ADDR + RSTCNTL_OFFSET, SW_RST_REQ_INIT);
389
390 return 0;
391 }
392 #endif
393
soc_runtime_setup(void)394 void soc_runtime_setup(void)
395 {
396 #ifdef NXP_WDOG_RESTART
397 request_intr_type_el3(BL31_NS_WDOG_WS1, wdog_interrupt_handler);
398 #endif
399 }
400
401 /* This function returns the total number of cores in the SoC. */
get_tot_num_cores(void)402 unsigned int get_tot_num_cores(void)
403 {
404 uint8_t num_clusters, cores_per_cluster;
405
406 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
407 return (num_clusters * cores_per_cluster);
408 }
409
410 /* This function returns the PMU IDLE Cluster mask. */
get_pmu_idle_cluster_mask(void)411 unsigned int get_pmu_idle_cluster_mask(void)
412 {
413 uint8_t num_clusters, cores_per_cluster;
414
415 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
416 return ((1 << num_clusters) - 2);
417 }
418
419 /* This function returns the PMU Flush Cluster mask. */
get_pmu_flush_cluster_mask(void)420 unsigned int get_pmu_flush_cluster_mask(void)
421 {
422 uint8_t num_clusters, cores_per_cluster;
423
424 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
425 return ((1 << num_clusters) - 2);
426 }
427
428 /* This function returns the PMU idle core mask. */
get_pmu_idle_core_mask(void)429 unsigned int get_pmu_idle_core_mask(void)
430 {
431 return ((1 << get_tot_num_cores()) - 2);
432 }
433
434 /* Function to return the SoC SYS CLK */
get_sys_clk(void)435 unsigned int get_sys_clk(void)
436 {
437 return NXP_SYSCLK_FREQ;
438 }
439 #endif
440