Tegra: fix trivial misra issues

Not having U or ULL as a suffix for these enums causes
a lot of unnecessary MISRA issues. This patch adds U or
ULL suffix to these common enums to reduce number of
MI

Tegra: fix trivial misra issues

Not having U or ULL as a suffix for these enums causes
a lot of unnecessary MISRA issues. This patch adds U or
ULL suffix to these common enums to reduce number of
MISRA issues.

Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: Add support for fake system suspend

This patch adds support for fake system suspend (SC7).
This is a debug mode, to ensure that a different code path is
executed for cases like pre-silicon de

Tegra: Add support for fake system suspend

This patch adds support for fake system suspend (SC7).
This is a debug mode, to ensure that a different code path is
executed for cases like pre-silicon development, where a
full-fledged SC7 is not possible in early stages.

This particular patch ensures that, if fake system suspend is
enabled (denoted by tegra_fake_system_suspend variable
having a non-zero value), instead of calling WFI, a request
for a warm reset is made for starting the SC7 exit procedure.

This ensures that the code path of kernel->ATF and back to
kernel is executed without depending on other components
involved in SC7 code path.

Additionally, this patch also adds support for SMC call
from kernel, enabling fake system suspend mode.

Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v1: disable AHB redirection after cold boot

During boot, USB3 and flash media (SDMMC/SATA) devices need access to
IRAM. Because these clients connect to the MC and do not have a direc

Tegra: memctrl_v1: disable AHB redirection after cold boot

During boot, USB3 and flash media (SDMMC/SATA) devices need access to
IRAM. Because these clients connect to the MC and do not have a direct
path to the IRAM, the MC implements AHB redirection during boot to allow
path to IRAM. In this mode, accesses to a programmed memory address aperture
are directed to the AHB bus, allowing access to the IRAM. The AHB aperture
is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are
initialized to disable this aperture. Once bootup is complete, we must
program IRAM base/top, thus disabling access to IRAM.

This patch provides functionality to disable this access. The tegra port
calls this new function before jumping to the non-secure world during
cold boot.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: platform: support Tegra186 chip id

This patch adds support to read the chip id and identify if
the current platform is Tegra186.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: smmu: support for multiple devices

This patch adds flexibility to the code to initialise multiple SMMU
devices. The base address macro name has been changed to make it
explicit that we suppor

Tegra: smmu: support for multiple devices

This patch adds flexibility to the code to initialise multiple SMMU
devices. The base address macro name has been changed to make it
explicit that we support multiple SMMUs.

Change-Id: Id4854fb010ebeb699512d79c769de24050c2ad69
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: smmu: platform handler for SMMU settings

This patch empowers the platforms to provide an array with the
registers that must be saved/restored across System Suspend.

Original-change-by: Prite

Tegra: smmu: platform handler for SMMU settings

This patch empowers the platforms to provide an array with the
registers that must be saved/restored across System Suspend.

Original-change-by: Pritesh Raithatha <praithatha@nvidia.com>

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v1: enable 'xlat_table_v2' library

This patch enables the 'xlat_table_v2' library for the Tegra Memory
Controller driver. This library allows us to dynamically map/unmap
memory region

Tegra: memctrl_v1: enable 'xlat_table_v2' library

This patch enables the 'xlat_table_v2' library for the Tegra Memory
Controller driver. This library allows us to dynamically map/unmap
memory regions, with MMU enabled.

The Memory Controller driver maps/unmaps non-overlapping Video Memory
region, to clean it of any secure contents, before it resizes the
region.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: platform handler for MC settings

This patch empowers the platforms to provide the settings (e.g. stream ID,
security setting, transaction overrides) required by the Memory Control

Tegra: memctrl_v2: platform handler for MC settings

This patch empowers the platforms to provide the settings (e.g. stream ID,
security setting, transaction overrides) required by the Memory Controller
driver. This allows the platforms to program the Memory Controller as per
their needs and makes the driver scalable.

Original-change-by: Pritesh Raithatha <praithatha@nvidia.com>

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: remove non-secure access to TZSRAM memory

This patch removes the memory controller configuration setting, which
allowed non-secure access to the TZSRAM memory.

Change-Id: Ic13645

Tegra: memctrl_v2: remove non-secure access to TZSRAM memory

This patch removes the memory controller configuration setting, which
allowed non-secure access to the TZSRAM memory.

Change-Id: Ic13645ba6a7694f192565962df40ca4fb8130f23
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: read activity monitor's clock counter values

This patch adds a new SMC function ID to read the refclk and coreclk
clock counter values from the Activity Monitor. The non-secure world
requi

Tegra186: read activity monitor's clock counter values

This patch adds a new SMC function ID to read the refclk and coreclk
clock counter values from the Activity Monitor. The non-secure world
requires this information to calculate the CPU's frequency.

Formula: "freq = (delta_coreclk / delta_refclk) * refclk_freq"

The following CPU registers have to be set by the non-secure driver
before issuing the SMC:

X1 = MPIDR of the target core
X2 = MIDR of the target core

Change-Id: I296d835def1f5788c17640c0c456b8f8f0e90824
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: move smmu driver to tegra/common

This patch moves the smmu driver introduced by the Tegra186 port
to tegra/common so that future chips can (re)use it.

Change-Id: Ia44c7f2a62fb2d8869db3a44

Tegra186: move smmu driver to tegra/common

This patch moves the smmu driver introduced by the Tegra186 port
to tegra/common so that future chips can (re)use it.

Change-Id: Ia44c7f2a62fb2d8869db3a44742a8c6b13c49036
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: split MCE driver into public/private interfaces

This patch splits the MCE driver into public and private interfaces
to allow usage of common functionality across multiple SoCs.

Change-Id:

Tegra186: split MCE driver into public/private interfaces

This patch splits the MCE driver into public and private interfaces
to allow usage of common functionality across multiple SoCs.

Change-Id: Ib58080e730d72f11ff79507d8e0acffb2ad5c606
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: move TSA macros to tegra_def.h

This patch moves the TSA block's macros from memctrl_v2.h to
tegra_def.h in the Tegra186 tree.

Change-Id: I8b45dd3905c5d1f33ffb36d8b2de72aeb06674aa
Signed-o

Tegra186: move TSA macros to tegra_def.h

This patch moves the TSA block's macros from memctrl_v2.h to
tegra_def.h in the Tegra186 tree.

Change-Id: I8b45dd3905c5d1f33ffb36d8b2de72aeb06674aa
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: drivers: memctrl: move chip specific defines to tegra_def.h

This patch moves the chip specific memory controller driver defines to
the appropriate tegra_def.h files, for future compatibility.

Tegra: drivers: memctrl: move chip specific defines to tegra_def.h

This patch moves the chip specific memory controller driver defines to
the appropriate tegra_def.h files, for future compatibility.

Change-Id: I3179fb771d8b32e913ca29bd94af95f4b2fc1961
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: move platform specific MCE defines to tegra_def.h

This patch moves the MCE's configurable parameters to tegra_def.h for
the Tegra186 SoC, to allow forward compatiblity.

Change-Id: If8660c

Tegra186: move platform specific MCE defines to tegra_def.h

This patch moves the MCE's configurable parameters to tegra_def.h for
the Tegra186 SoC, to allow forward compatiblity.

Change-Id: If8660c1c09908a4064dbb67d5ca4fb78389cab13
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: save TZDRAM settings to secure scratch registers

Save TZDRAM settings for SC7 resume firmware to restore.

SECURITY_BOM: MC_SECURITY_CFG0_0 = SECURE_RSV55_SCRATCH_0
SECURITY_B

Tegra: memctrl_v2: save TZDRAM settings to secure scratch registers

Save TZDRAM settings for SC7 resume firmware to restore.

SECURITY_BOM: MC_SECURITY_CFG0_0 = SECURE_RSV55_SCRATCH_0
SECURITY_BOM_HI: MC_SECURITY_CFG3_0 = SECURE_RSV55_SCRATCH_1
SECURITY_SIZE_MB: MC_SECURITY_CFG1_0 = SECURE_RSV54_SCRATCH_1

Change-Id: I78e891d9ebf576ff2a17ff87cf3aff4030ee11b8
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: use helper functions to get major/minor version

This patch uses helper functions to read the chips's major and minor
version values.

Change-Id: I5b2530a31af5ab3778a8aa63380def4e9f9ee6ec
S

Tegra186: use helper functions to get major/minor version

This patch uses helper functions to read the chips's major and minor
version values.

Change-Id: I5b2530a31af5ab3778a8aa63380def4e9f9ee6ec
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: smmu: disable TCU prefetch for all the 64 contexts

This patch disables TCU prefetch for all the contexts in order
to improve SMMU performance.

Change-Id: I82ca49a0e396d9f064f5c62a5f00c4b2101

Tegra: smmu: disable TCU prefetch for all the 64 contexts

This patch disables TCU prefetch for all the contexts in order
to improve SMMU performance.

Change-Id: I82ca49a0e396d9f064f5c62a5f00c4b2101d8459
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: handlers to get BL31 arguments from previous bootloader

This patch overrides the default handlers to get BL31 arguments from the
previous bootloader. The previous bootloader stores the poi

Tegra186: handlers to get BL31 arguments from previous bootloader

This patch overrides the default handlers to get BL31 arguments from the
previous bootloader. The previous bootloader stores the pointer to the
arguments in PMC secure scratch register #53.

BL31 is the first component running on the CPU, as there isn't a previous
bootloader. We set the RESET_TO_BL31 flag to enable the path which assumes
that there are no input parameters passed by the previous bootloader.

Change-Id: Idacc1df292a70c9c1cb4d5c3a774bd796175d5e8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: TZRAM aperture configuration settings

This patch enables the configuration settings for the TZRAM
aperture by programming the base/size of the aperture and
restricting access to i

Tegra: memctrl_v2: TZRAM aperture configuration settings

This patch enables the configuration settings for the TZRAM
aperture by programming the base/size of the aperture and
restricting access to it. We allow only the CPU to read/write
by programming the access configuration registers to 0.

Change-Id: Ie16ad29f4c5ec7aafa972b0a0230b4790ad5619e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: Enable ECC and Parity Protection for A02p SKUs

This patch enables ECC and Parity Protection for Cortex-A57 CPUs during boot,
for Tegra186 A02p SKUs.

Change-Id: I8522a6cb61f5e4fa9e0471f558

Tegra186: Enable ECC and Parity Protection for A02p SKUs

This patch enables ECC and Parity Protection for Cortex-A57 CPUs during boot,
for Tegra186 A02p SKUs.

Change-Id: I8522a6cb61f5e4fa9e0471f558a0c3ee8078370e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: fix recursion in included headers (tegra_def.h/platform_def.h)

This patch fixes the "Recursion in included headers" error flagged by
Coverity.

Fixes coverity errors "31858: Recursion in i

Tegra186: fix recursion in included headers (tegra_def.h/platform_def.h)

This patch fixes the "Recursion in included headers" error flagged by
Coverity.

Fixes coverity errors "31858: Recursion in included headers" and
"31857: Recursion in included headers"

Change-Id: Icf8838434b1808b396e743e47f59adc452546364
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: enable support for simulation environment

The Tegra simulation environment has limited capabilities. This patch
checks the chip's major and minor versions to decide the features to
enable/

Tegra186: enable support for simulation environment

The Tegra simulation environment has limited capabilities. This patch
checks the chip's major and minor versions to decide the features to
enable/disable - MCE firmware version checking is disabled and limited
Memory Controller settings are enabled

Change-Id: I258a807cc3b83cdff14a9975b4ab4f9d1a9d7dcf
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: save/restore BL31 context to/from TZDRAM

This patch adds support to save the BL31 state to the TZDRAM
before entering system suspend. The TZRAM loses state during
system suspend and so we

Tegra186: save/restore BL31 context to/from TZDRAM

This patch adds support to save the BL31 state to the TZDRAM
before entering system suspend. The TZRAM loses state during
system suspend and so we need to copy the entire BL31 code to
TZDRAM before entering the state.

In order to restore the state on exiting system suspend, a new
CPU reset handler is implemented which gets copied to TZDRAM
during boot. TO keep things simple we use this same reset handler
for booting secondary CPUs too.

Change-Id: I770f799c255d22279b5cdb9b4d587d3a4c54fad7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: re-configure MSS' client settings

This patch reprograms MSS to make ROC deal with ordering of
MC traffic after boot and system suspend exit. This is needed
as device boots with MSS having

Tegra186: re-configure MSS' client settings

This patch reprograms MSS to make ROC deal with ordering of
MC traffic after boot and system suspend exit. This is needed
as device boots with MSS having all control but POR wants ROC
to deal with the ordering. Performance is expected to improve
with ROC but since no one has really tested the performance,
keep the option configurable for now by introducing a platform
level makefile variable.

Change-Id: I2e782fea138ccf9d281eb043a6b2c3bb97c839a7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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