1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <bl31.h> 34 #include <bl_common.h> 35 #include <console.h> 36 #include <context.h> 37 #include <context_mgmt.h> 38 #include <cortex_a57.h> 39 #include <debug.h> 40 #include <denver.h> 41 #include <interrupt_mgmt.h> 42 #include <mce.h> 43 #include <platform.h> 44 #include <tegra_def.h> 45 #include <tegra_platform.h> 46 #include <tegra_private.h> 47 #include <xlat_tables.h> 48 49 DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1) 50 extern uint64_t tegra_enable_l2_ecc_parity_prot; 51 52 /******************************************************************************* 53 * The Tegra power domain tree has a single system level power domain i.e. a 54 * single root node. The first entry in the power domain descriptor specifies 55 * the number of power domains at the highest power level. 56 ******************************************************************************* 57 */ 58 const unsigned char tegra_power_domain_tree_desc[] = { 59 /* No of root nodes */ 60 1, 61 /* No of clusters */ 62 PLATFORM_CLUSTER_COUNT, 63 /* No of CPU cores - cluster0 */ 64 PLATFORM_MAX_CPUS_PER_CLUSTER, 65 /* No of CPU cores - cluster1 */ 66 PLATFORM_MAX_CPUS_PER_CLUSTER 67 }; 68 69 /* 70 * Table of regions to map using the MMU. 71 */ 72 static const mmap_region_t tegra_mmap[] = { 73 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 74 MT_DEVICE | MT_RW | MT_SECURE), 75 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ 76 MT_DEVICE | MT_RW | MT_SECURE), 77 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 78 MT_DEVICE | MT_RW | MT_SECURE), 79 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 80 MT_DEVICE | MT_RW | MT_SECURE), 81 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/ 82 MT_DEVICE | MT_RW | MT_SECURE), 83 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */ 84 MT_DEVICE | MT_RW | MT_SECURE), 85 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */ 86 MT_DEVICE | MT_RW | MT_SECURE), 87 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ 88 MT_DEVICE | MT_RW | MT_SECURE), 89 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 90 MT_DEVICE | MT_RW | MT_SECURE), 91 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ 92 MT_DEVICE | MT_RW | MT_SECURE), 93 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ 94 MT_DEVICE | MT_RW | MT_SECURE), 95 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ 96 MT_DEVICE | MT_RW | MT_SECURE), 97 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 98 MT_DEVICE | MT_RW | MT_SECURE), 99 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 100 MT_DEVICE | MT_RW | MT_SECURE), 101 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ 102 MT_DEVICE | MT_RW | MT_SECURE), 103 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 104 MT_DEVICE | MT_RW | MT_SECURE), 105 MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000, /* 128KB - ARM/Denver */ 106 MT_DEVICE | MT_RW | MT_SECURE), 107 MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x1000000, /* 64KB */ 108 MT_DEVICE | MT_RW | MT_SECURE), 109 {0} 110 }; 111 112 /******************************************************************************* 113 * Set up the pagetables as per the platform memory map & initialize the MMU 114 ******************************************************************************/ 115 const mmap_region_t *plat_get_mmio_map(void) 116 { 117 /* MMIO space */ 118 return tegra_mmap; 119 } 120 121 /******************************************************************************* 122 * Handler to get the System Counter Frequency 123 ******************************************************************************/ 124 unsigned int plat_get_syscnt_freq2(void) 125 { 126 return 31250000; 127 } 128 129 /******************************************************************************* 130 * Maximum supported UART controllers 131 ******************************************************************************/ 132 #define TEGRA186_MAX_UART_PORTS 7 133 134 /******************************************************************************* 135 * This variable holds the UART port base addresses 136 ******************************************************************************/ 137 static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 138 0, /* undefined - treated as an error case */ 139 TEGRA_UARTA_BASE, 140 TEGRA_UARTB_BASE, 141 TEGRA_UARTC_BASE, 142 TEGRA_UARTD_BASE, 143 TEGRA_UARTE_BASE, 144 TEGRA_UARTF_BASE, 145 TEGRA_UARTG_BASE, 146 }; 147 148 /******************************************************************************* 149 * Retrieve the UART controller base to be used as the console 150 ******************************************************************************/ 151 uint32_t plat_get_console_from_id(int id) 152 { 153 if (id > TEGRA186_MAX_UART_PORTS) 154 return 0; 155 156 return tegra186_uart_addresses[id]; 157 } 158 159 /* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */ 160 #define TEGRA186_VER_A02P 0x1201 161 162 /******************************************************************************* 163 * Handler for early platform setup 164 ******************************************************************************/ 165 void plat_early_platform_setup(void) 166 { 167 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 168 uint32_t chip_subrev, val; 169 170 /* sanity check MCE firmware compatibility */ 171 mce_verify_firmware_version(); 172 173 /* 174 * Enable ECC and Parity Protection for Cortex-A57 CPUs 175 * for Tegra A02p SKUs 176 */ 177 if (impl != DENVER_IMPL) { 178 179 /* get the major, minor and sub-version values */ 180 chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) & 181 SUBREVISION_MASK; 182 183 /* prepare chip version number */ 184 val = (tegra_get_chipid_major() << 12) | 185 (tegra_get_chipid_minor() << 8) | 186 chip_subrev; 187 188 /* enable L2 ECC for Tegra186 A02P and beyond */ 189 if (val >= TEGRA186_VER_A02P) { 190 191 val = read_l2ctlr_el1(); 192 val |= L2_ECC_PARITY_PROTECTION_BIT; 193 write_l2ctlr_el1(val); 194 195 /* 196 * Set the flag to enable ECC/Parity Protection 197 * when we exit System Suspend or Cluster Powerdn 198 */ 199 tegra_enable_l2_ecc_parity_prot = 1; 200 } 201 } 202 } 203 204 /* Secure IRQs for Tegra186 */ 205 static const irq_sec_cfg_t tegra186_sec_irqs[] = { 206 { 207 TEGRA186_TOP_WDT_IRQ, 208 TEGRA186_SEC_IRQ_TARGET_MASK, 209 INTR_TYPE_EL3, 210 }, 211 { 212 TEGRA186_AON_WDT_IRQ, 213 TEGRA186_SEC_IRQ_TARGET_MASK, 214 INTR_TYPE_EL3, 215 }, 216 }; 217 218 /******************************************************************************* 219 * Initialize the GIC and SGIs 220 ******************************************************************************/ 221 void plat_gic_setup(void) 222 { 223 tegra_gic_setup(tegra186_sec_irqs, 224 sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); 225 226 /* 227 * Initialize the FIQ handler only if the platform supports any 228 * FIQ interrupt sources. 229 */ 230 if (sizeof(tegra186_sec_irqs) > 0) 231 tegra_fiq_handler_setup(); 232 } 233 234 /******************************************************************************* 235 * Return pointer to the BL31 params from previous bootloader 236 ******************************************************************************/ 237 bl31_params_t *plat_get_bl31_params(void) 238 { 239 uint32_t val; 240 241 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); 242 243 return (bl31_params_t *)(uintptr_t)val; 244 } 245 246 /******************************************************************************* 247 * Return pointer to the BL31 platform params from previous bootloader 248 ******************************************************************************/ 249 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 250 { 251 uint32_t val; 252 253 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); 254 255 return (plat_params_from_bl2_t *)(uintptr_t)val; 256 } 257