1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __MEMCTRLV2_H__ 32 #define __MEMCTRLV2_H__ 33 34 #include <mmio.h> 35 #include <tegra_def.h> 36 37 /******************************************************************************* 38 * StreamID to indicate no SMMU translations (requests to be steered on the 39 * SMMU bypass path) 40 ******************************************************************************/ 41 #define MC_STREAM_ID_MAX 0x7F 42 43 /******************************************************************************* 44 * Stream ID Override Config registers 45 ******************************************************************************/ 46 #define MC_STREAMID_OVERRIDE_CFG_PTCR 0x0 47 #define MC_STREAMID_OVERRIDE_CFG_AFIR 0x70 48 #define MC_STREAMID_OVERRIDE_CFG_HDAR 0xA8 49 #define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0xB0 50 #define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0xE0 51 #define MC_STREAMID_OVERRIDE_CFG_SATAR 0xF8 52 #define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138 53 #define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158 54 #define MC_STREAMID_OVERRIDE_CFG_AFIW 0x188 55 #define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8 56 #define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1C8 57 #define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8 58 #define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8 59 #define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220 60 #define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230 61 #define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238 62 #define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250 63 #define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258 64 #define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260 65 #define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268 66 #define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2A0 67 #define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2A8 68 #define MC_STREAMID_OVERRIDE_CFG_GPUSRD 0x2C0 69 #define MC_STREAMID_OVERRIDE_CFG_GPUSWR 0x2C8 70 #define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300 71 #define MC_STREAMID_OVERRIDE_CFG_SDMMCRAA 0x308 72 #define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310 73 #define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318 74 #define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320 75 #define MC_STREAMID_OVERRIDE_CFG_SDMMCWAA 0x328 76 #define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330 77 #define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338 78 #define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360 79 #define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368 80 #define MC_STREAMID_OVERRIDE_CFG_VIW 0x390 81 #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3C0 82 #define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3C8 83 #define MC_STREAMID_OVERRIDE_CFG_APER 0x3D0 84 #define MC_STREAMID_OVERRIDE_CFG_APEW 0x3D8 85 #define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3F0 86 #define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3F8 87 #define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400 88 #define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408 89 #define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420 90 #define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428 91 #define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430 92 #define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438 93 #define MC_STREAMID_OVERRIDE_CFG_GPUSRD2 0x440 94 #define MC_STREAMID_OVERRIDE_CFG_GPUSWR2 0x448 95 #define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460 96 #define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468 97 #define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470 98 #define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478 99 #define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480 100 #define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488 101 #define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490 102 #define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498 103 #define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4A0 104 #define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4A8 105 #define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4B0 106 #define MC_STREAMID_OVERRIDE_CFG_AONR 0x4B8 107 #define MC_STREAMID_OVERRIDE_CFG_AONW 0x4C0 108 #define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4C8 109 #define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4D0 110 #define MC_STREAMID_OVERRIDE_CFG_SCER 0x4D8 111 #define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4E0 112 #define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4E8 113 #define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4F0 114 #define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4F8 115 #define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500 116 #define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508 117 #define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510 118 #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518 119 120 /******************************************************************************* 121 * Stream ID Security Config registers 122 ******************************************************************************/ 123 #define MC_STREAMID_SECURITY_CFG_PTCR 0x4 124 #define MC_STREAMID_SECURITY_CFG_AFIR 0x74 125 #define MC_STREAMID_SECURITY_CFG_HDAR 0xAC 126 #define MC_STREAMID_SECURITY_CFG_HOST1XDMAR 0xB4 127 #define MC_STREAMID_SECURITY_CFG_NVENCSRD 0xE4 128 #define MC_STREAMID_SECURITY_CFG_SATAR 0xFC 129 #define MC_STREAMID_SECURITY_CFG_HDAW 0x1AC 130 #define MC_STREAMID_SECURITY_CFG_MPCORER 0x13C 131 #define MC_STREAMID_SECURITY_CFG_NVENCSWR 0x15C 132 #define MC_STREAMID_SECURITY_CFG_AFIW 0x18C 133 #define MC_STREAMID_SECURITY_CFG_MPCOREW 0x1CC 134 #define MC_STREAMID_SECURITY_CFG_SATAW 0x1EC 135 #define MC_STREAMID_SECURITY_CFG_ISPRA 0x224 136 #define MC_STREAMID_SECURITY_CFG_ISPWA 0x234 137 #define MC_STREAMID_SECURITY_CFG_ISPWB 0x23C 138 #define MC_STREAMID_SECURITY_CFG_XUSB_HOSTR 0x254 139 #define MC_STREAMID_SECURITY_CFG_XUSB_HOSTW 0x25C 140 #define MC_STREAMID_SECURITY_CFG_XUSB_DEVR 0x264 141 #define MC_STREAMID_SECURITY_CFG_XUSB_DEVW 0x26C 142 #define MC_STREAMID_SECURITY_CFG_TSECSRD 0x2A4 143 #define MC_STREAMID_SECURITY_CFG_TSECSWR 0x2AC 144 #define MC_STREAMID_SECURITY_CFG_GPUSRD 0x2C4 145 #define MC_STREAMID_SECURITY_CFG_GPUSWR 0x2CC 146 #define MC_STREAMID_SECURITY_CFG_SDMMCRA 0x304 147 #define MC_STREAMID_SECURITY_CFG_SDMMCRAA 0x30C 148 #define MC_STREAMID_SECURITY_CFG_SDMMCR 0x314 149 #define MC_STREAMID_SECURITY_CFG_SDMMCRAB 0x31C 150 #define MC_STREAMID_SECURITY_CFG_SDMMCWA 0x324 151 #define MC_STREAMID_SECURITY_CFG_SDMMCWAA 0x32C 152 #define MC_STREAMID_SECURITY_CFG_SDMMCW 0x334 153 #define MC_STREAMID_SECURITY_CFG_SDMMCWAB 0x33C 154 #define MC_STREAMID_SECURITY_CFG_VICSRD 0x364 155 #define MC_STREAMID_SECURITY_CFG_VICSWR 0x36C 156 #define MC_STREAMID_SECURITY_CFG_VIW 0x394 157 #define MC_STREAMID_SECURITY_CFG_NVDECSRD 0x3C4 158 #define MC_STREAMID_SECURITY_CFG_NVDECSWR 0x3CC 159 #define MC_STREAMID_SECURITY_CFG_APER 0x3D4 160 #define MC_STREAMID_SECURITY_CFG_APEW 0x3DC 161 #define MC_STREAMID_SECURITY_CFG_NVJPGSRD 0x3F4 162 #define MC_STREAMID_SECURITY_CFG_NVJPGSWR 0x3FC 163 #define MC_STREAMID_SECURITY_CFG_SESRD 0x404 164 #define MC_STREAMID_SECURITY_CFG_SESWR 0x40C 165 #define MC_STREAMID_SECURITY_CFG_ETRR 0x424 166 #define MC_STREAMID_SECURITY_CFG_ETRW 0x42C 167 #define MC_STREAMID_SECURITY_CFG_TSECSRDB 0x434 168 #define MC_STREAMID_SECURITY_CFG_TSECSWRB 0x43C 169 #define MC_STREAMID_SECURITY_CFG_GPUSRD2 0x444 170 #define MC_STREAMID_SECURITY_CFG_GPUSWR2 0x44C 171 #define MC_STREAMID_SECURITY_CFG_AXISR 0x464 172 #define MC_STREAMID_SECURITY_CFG_AXISW 0x46C 173 #define MC_STREAMID_SECURITY_CFG_EQOSR 0x474 174 #define MC_STREAMID_SECURITY_CFG_EQOSW 0x47C 175 #define MC_STREAMID_SECURITY_CFG_UFSHCR 0x484 176 #define MC_STREAMID_SECURITY_CFG_UFSHCW 0x48C 177 #define MC_STREAMID_SECURITY_CFG_NVDISPLAYR 0x494 178 #define MC_STREAMID_SECURITY_CFG_BPMPR 0x49C 179 #define MC_STREAMID_SECURITY_CFG_BPMPW 0x4A4 180 #define MC_STREAMID_SECURITY_CFG_BPMPDMAR 0x4AC 181 #define MC_STREAMID_SECURITY_CFG_BPMPDMAW 0x4B4 182 #define MC_STREAMID_SECURITY_CFG_AONR 0x4BC 183 #define MC_STREAMID_SECURITY_CFG_AONW 0x4C4 184 #define MC_STREAMID_SECURITY_CFG_AONDMAR 0x4CC 185 #define MC_STREAMID_SECURITY_CFG_AONDMAW 0x4D4 186 #define MC_STREAMID_SECURITY_CFG_SCER 0x4DC 187 #define MC_STREAMID_SECURITY_CFG_SCEW 0x4E4 188 #define MC_STREAMID_SECURITY_CFG_SCEDMAR 0x4EC 189 #define MC_STREAMID_SECURITY_CFG_SCEDMAW 0x4F4 190 #define MC_STREAMID_SECURITY_CFG_APEDMAR 0x4FC 191 #define MC_STREAMID_SECURITY_CFG_APEDMAW 0x504 192 #define MC_STREAMID_SECURITY_CFG_NVDISPLAYR1 0x50C 193 #define MC_STREAMID_SECURITY_CFG_VICSRD1 0x514 194 #define MC_STREAMID_SECURITY_CFG_NVDECSRD1 0x51C 195 196 /******************************************************************************* 197 * Memory Controller SMMU Bypass config register 198 ******************************************************************************/ 199 #define MC_SMMU_BYPASS_CONFIG 0x1820 200 #define MC_SMMU_BYPASS_CTRL_MASK 0x3 201 #define MC_SMMU_BYPASS_CTRL_SHIFT 0 202 #define MC_SMMU_CTRL_TBU_BYPASS_ALL (0 << MC_SMMU_BYPASS_CTRL_SHIFT) 203 #define MC_SMMU_CTRL_TBU_RSVD (1 << MC_SMMU_BYPASS_CTRL_SHIFT) 204 #define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2 << MC_SMMU_BYPASS_CTRL_SHIFT) 205 #define MC_SMMU_CTRL_TBU_BYPASS_NONE (3 << MC_SMMU_BYPASS_CTRL_SHIFT) 206 #define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1 << 31) 207 #define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \ 208 MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID) 209 210 /******************************************************************************* 211 * Memory Controller transaction override config registers 212 ******************************************************************************/ 213 #define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8 214 #define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0 215 #define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000 216 #define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490 217 #define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478 218 #define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8 219 #define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220 220 #define MC_TXN_OVERRIDE_CONFIG_SDMMCWAA 0x1328 221 #define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360 222 #define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8 223 #define MC_TXN_OVERRIDE_CONFIG_GPUSRD 0x12c0 224 #define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460 225 #define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0 226 #define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330 227 #define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470 228 #define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8 229 #define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0 230 #define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318 231 #define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510 232 #define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8 233 #define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390 234 #define MC_TXN_OVERRIDE_CONFIG_SDMMCRAA 0x1308 235 #define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468 236 #define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260 237 #define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480 238 #define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8 239 #define MC_TXN_OVERRIDE_CONFIG_GPUSWR 0x12c8 240 #define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8 241 #define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258 242 #define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438 243 #define MC_TXN_OVERRIDE_CONFIG_GPUSRD2 0x1440 244 #define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8 245 #define MC_TXN_OVERRIDE_CONFIG_GPUSWR2 0x1448 246 #define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0 247 #define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500 248 #define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0 249 #define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0 250 #define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420 251 #define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408 252 #define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0 253 #define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0 254 #define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430 255 #define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0 256 #define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0 257 #define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518 258 #define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250 259 #define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230 260 #define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400 261 #define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8 262 #define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8 263 #define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138 264 #define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320 265 #define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8 266 #define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8 267 #define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488 268 #define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8 269 #define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8 270 #define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428 271 #define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368 272 #define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158 273 #define MC_TXN_OVERRIDE_CONFIG_AFIR 0x1070 274 #define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338 275 #define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300 276 #define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508 277 #define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238 278 #define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498 279 #define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8 280 #define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310 281 #define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268 282 #define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0 283 #define MC_TXN_OVERRIDE_CONFIG_AFIW 0x1188 284 #define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0 285 286 #define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1 << 0) 287 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2 << 4) 288 #define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1 << 12) 289 290 /******************************************************************************* 291 * Non-SO_DEV transactions override values for CGID_TAG bitfield for the 292 * MC_TXN_OVERRIDE_CONFIG_{module} registers 293 ******************************************************************************/ 294 #define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0 295 #define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1 296 #define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2 297 #define MC_TXN_OVERRIDE_CGID_TAG_ADR 3 298 #define MC_TXN_OVERRIDE_CGID_TAG_MASK 3 299 300 /******************************************************************************* 301 * Structure to hold the transaction override settings to use to override 302 * client inputs 303 ******************************************************************************/ 304 typedef struct mc_txn_override_cfg { 305 uint32_t offset; 306 uint8_t cgid_tag; 307 } mc_txn_override_cfg_t; 308 309 #define mc_make_txn_override_cfg(off, val) \ 310 { \ 311 .offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \ 312 .cgid_tag = MC_TXN_OVERRIDE_ ## val \ 313 } 314 315 /******************************************************************************* 316 * Structure to hold the Stream ID to use to override client inputs 317 ******************************************************************************/ 318 typedef struct mc_streamid_override_cfg { 319 uint32_t offset; 320 uint8_t stream_id; 321 } mc_streamid_override_cfg_t; 322 323 /******************************************************************************* 324 * Structure to hold the Stream ID Security Configuration settings 325 ******************************************************************************/ 326 typedef struct mc_streamid_security_cfg { 327 char *name; 328 uint32_t offset; 329 int override_enable; 330 int override_client_inputs; 331 int override_client_ns_flag; 332 } mc_streamid_security_cfg_t; 333 334 #define OVERRIDE_DISABLE 1 335 #define OVERRIDE_ENABLE 0 336 #define CLIENT_FLAG_SECURE 0 337 #define CLIENT_FLAG_NON_SECURE 1 338 #define CLIENT_INPUTS_OVERRIDE 1 339 #define CLIENT_INPUTS_NO_OVERRIDE 0 340 341 #define mc_make_sec_cfg(off, ns, ovrrd, access) \ 342 { \ 343 .name = # off, \ 344 .offset = MC_STREAMID_SECURITY_CFG_ ## off, \ 345 .override_client_ns_flag = CLIENT_FLAG_ ## ns, \ 346 .override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \ 347 .override_enable = OVERRIDE_ ## access \ 348 } 349 350 /******************************************************************************* 351 * TZDRAM carveout configuration registers 352 ******************************************************************************/ 353 #define MC_SECURITY_CFG0_0 0x70 354 #define MC_SECURITY_CFG1_0 0x74 355 #define MC_SECURITY_CFG3_0 0x9BC 356 357 /******************************************************************************* 358 * Video Memory carveout configuration registers 359 ******************************************************************************/ 360 #define MC_VIDEO_PROTECT_BASE_HI 0x978 361 #define MC_VIDEO_PROTECT_BASE_LO 0x648 362 #define MC_VIDEO_PROTECT_SIZE_MB 0x64c 363 364 /******************************************************************************* 365 * TZRAM carveout configuration registers 366 ******************************************************************************/ 367 #define MC_TZRAM_BASE 0x1850 368 #define MC_TZRAM_END 0x1854 369 #define MC_TZRAM_HI_ADDR_BITS 0x1588 370 #define TZRAM_ADDR_HI_BITS_MASK 0x3 371 #define TZRAM_END_HI_BITS_SHIFT 8 372 #define MC_TZRAM_REG_CTRL 0x185c 373 #define DISABLE_TZRAM_ACCESS 1 374 375 /******************************************************************************* 376 * Memory Controller Reset Control registers 377 ******************************************************************************/ 378 #define MC_CLIENT_HOTRESET_CTRL0 0x200 379 #define MC_CLIENT_HOTRESET_CTRL0_RESET_VAL 0 380 #define MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB (1 << 0) 381 #define MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB (1 << 6) 382 #define MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB (1 << 7) 383 #define MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB (1 << 8) 384 #define MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB (1 << 9) 385 #define MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB (1 << 11) 386 #define MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB (1 << 15) 387 #define MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB (1 << 17) 388 #define MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB (1 << 18) 389 #define MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB (1 << 19) 390 #define MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB (1 << 20) 391 #define MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB (1 << 22) 392 #define MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB (1 << 29) 393 #define MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB (1 << 30) 394 #define MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB (1 << 31) 395 #define MC_CLIENT_HOTRESET_STATUS0 0x204 396 #define MC_CLIENT_HOTRESET_CTRL1 0x970 397 #define MC_CLIENT_HOTRESET_CTRL1_RESET_VAL 0 398 #define MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB (1 << 0) 399 #define MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB (1 << 2) 400 #define MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB (1 << 5) 401 #define MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB (1 << 6) 402 #define MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB (1 << 7) 403 #define MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB (1 << 8) 404 #define MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB (1 << 12) 405 #define MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB (1 << 13) 406 #define MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB (1 << 18) 407 #define MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB (1 << 19) 408 #define MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB (1 << 20) 409 #define MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB (1 << 21) 410 #define MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB (1 << 22) 411 #define MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB (1 << 23) 412 #define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1 << 24) 413 #define MC_CLIENT_HOTRESET_STATUS1 0x974 414 415 /******************************************************************************* 416 * TSA configuration registers 417 ******************************************************************************/ 418 #define TSA_CONFIG_STATIC0_CSW_SESWR 0x4010 419 #define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100 420 #define TSA_CONFIG_STATIC0_CSW_ETRW 0x4038 421 #define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100 422 #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5010 423 #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100 424 #define TSA_CONFIG_STATIC0_CSW_AXISW 0x7008 425 #define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100 426 #define TSA_CONFIG_STATIC0_CSW_HDAW 0xA008 427 #define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x100 428 #define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xB018 429 #define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100 430 #define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0xD018 431 #define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100 432 #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0xD028 433 #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100 434 #define TSA_CONFIG_STATIC0_CSW_APEDMAW 0x12018 435 #define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100 436 #define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x13008 437 #define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100 438 #define TSA_CONFIG_STATIC0_CSW_AFIW 0x13018 439 #define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100 440 #define TSA_CONFIG_STATIC0_CSW_SATAW 0x13028 441 #define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100 442 #define TSA_CONFIG_STATIC0_CSW_EQOSW 0x13038 443 #define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100 444 #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x15008 445 #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100 446 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x15018 447 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100 448 449 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11) 450 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11) 451 452 /******************************************************************************* 453 * Memory Controller's PCFIFO client configuration registers 454 ******************************************************************************/ 455 #define MC_PCFIFO_CLIENT_CONFIG1 0xdd4 456 #define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20000 457 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0 << 17) 458 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1 << 17) 459 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0 << 21) 460 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1 << 21) 461 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0 << 29) 462 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1 << 29) 463 464 #define MC_PCFIFO_CLIENT_CONFIG2 0xdd8 465 #define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x20000 466 #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0 << 11) 467 #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1 << 11) 468 #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0 << 13) 469 #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1 << 13) 470 471 #define MC_PCFIFO_CLIENT_CONFIG3 0xddc 472 #define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0 473 #define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0 << 7) 474 #define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1 << 7) 475 476 #define MC_PCFIFO_CLIENT_CONFIG4 0xde0 477 #define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0 478 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0 << 1) 479 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1 << 1) 480 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0 << 5) 481 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1 << 5) 482 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0 << 13) 483 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1 << 13) 484 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0 << 15) 485 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1 << 15) 486 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0 << 17) 487 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1 << 17) 488 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0 << 22) 489 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1 << 22) 490 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0 << 26) 491 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1 << 26) 492 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0 << 30) 493 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1 << 30) 494 495 #define MC_PCFIFO_CLIENT_CONFIG5 0xbf4 496 #define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0 497 #define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0 << 0) 498 #define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1 << 0) 499 500 /******************************************************************************* 501 * Memory Controller's SMMU client configuration registers 502 ******************************************************************************/ 503 #define MC_SMMU_CLIENT_CONFIG1 0x44 504 #define MC_SMMU_CLIENT_CONFIG1_RESET_VAL 0x20000 505 #define MC_SMMU_CLIENT_CONFIG1_AFIW_UNORDERED (0 << 17) 506 #define MC_SMMU_CLIENT_CONFIG1_AFIW_MASK (1 << 17) 507 #define MC_SMMU_CLIENT_CONFIG1_HDAW_UNORDERED (0 << 21) 508 #define MC_SMMU_CLIENT_CONFIG1_HDAW_MASK (1 << 21) 509 #define MC_SMMU_CLIENT_CONFIG1_SATAW_UNORDERED (0 << 29) 510 #define MC_SMMU_CLIENT_CONFIG1_SATAW_MASK (1 << 29) 511 512 #define MC_SMMU_CLIENT_CONFIG2 0x48 513 #define MC_SMMU_CLIENT_CONFIG2_RESET_VAL 0x20000 514 #define MC_SMMU_CLIENT_CONFIG2_XUSB_HOSTW_UNORDERED (0 << 11) 515 #define MC_SMMU_CLIENT_CONFIG2_XUSB_HOSTW_MASK (1 << 11) 516 #define MC_SMMU_CLIENT_CONFIG2_XUSB_DEVW_UNORDERED (0 << 13) 517 #define MC_SMMU_CLIENT_CONFIG2_XUSB_DEVW_MASK (1 << 13) 518 519 #define MC_SMMU_CLIENT_CONFIG3 0x4c 520 #define MC_SMMU_CLIENT_CONFIG3_RESET_VAL 0 521 #define MC_SMMU_CLIENT_CONFIG3_SDMMCWAB_UNORDERED (0 << 7) 522 #define MC_SMMU_CLIENT_CONFIG3_SDMMCWAB_MASK (1 << 7) 523 524 #define MC_SMMU_CLIENT_CONFIG4 0xb9c 525 #define MC_SMMU_CLIENT_CONFIG4_RESET_VAL 0 526 #define MC_SMMU_CLIENT_CONFIG4_SESWR_UNORDERED (0 << 1) 527 #define MC_SMMU_CLIENT_CONFIG4_SESWR_MASK (1 << 1) 528 #define MC_SMMU_CLIENT_CONFIG4_ETRW_UNORDERED (0 << 5) 529 #define MC_SMMU_CLIENT_CONFIG4_ETRW_MASK (1 << 5) 530 #define MC_SMMU_CLIENT_CONFIG4_AXISW_UNORDERED (0 << 13) 531 #define MC_SMMU_CLIENT_CONFIG4_AXISW_MASK (1 << 13) 532 #define MC_SMMU_CLIENT_CONFIG4_EQOSW_UNORDERED (0 << 15) 533 #define MC_SMMU_CLIENT_CONFIG4_EQOSW_MASK (1 << 15) 534 #define MC_SMMU_CLIENT_CONFIG4_UFSHCW_UNORDERED (0 << 17) 535 #define MC_SMMU_CLIENT_CONFIG4_UFSHCW_MASK (1 << 17) 536 #define MC_SMMU_CLIENT_CONFIG4_BPMPDMAW_UNORDERED (0 << 22) 537 #define MC_SMMU_CLIENT_CONFIG4_BPMPDMAW_MASK (1 << 22) 538 #define MC_SMMU_CLIENT_CONFIG4_AONDMAW_UNORDERED (0 << 26) 539 #define MC_SMMU_CLIENT_CONFIG4_AONDMAW_MASK (1 << 26) 540 #define MC_SMMU_CLIENT_CONFIG4_SCEDMAW_UNORDERED (0 << 30) 541 #define MC_SMMU_CLIENT_CONFIG4_SCEDMAW_MASK (1 << 30) 542 543 #define MC_SMMU_CLIENT_CONFIG5 0xbac 544 #define MC_SMMU_CLIENT_CONFIG5_RESET_VAL 0 545 #define MC_SMMU_CLIENT_CONFIG5_APEDMAW_UNORDERED (0 << 0) 546 #define MC_SMMU_CLIENT_CONFIG5_APEDMAW_MASK (1 << 0) 547 548 static inline uint32_t tegra_mc_read_32(uint32_t off) 549 { 550 return mmio_read_32(TEGRA_MC_BASE + off); 551 } 552 553 static inline void tegra_mc_write_32(uint32_t off, uint32_t val) 554 { 555 mmio_write_32(TEGRA_MC_BASE + off, val); 556 } 557 558 static inline uint32_t tegra_mc_streamid_read_32(uint32_t off) 559 { 560 return mmio_read_32(TEGRA_MC_STREAMID_BASE + off); 561 } 562 563 static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val) 564 { 565 mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val); 566 } 567 568 #define mc_set_pcfifo_unordered_boot_so_mss(id, client) \ 569 (~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \ 570 MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED) 571 572 #define mc_set_smmu_unordered_boot_so_mss(id, client) \ 573 (~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \ 574 MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED) 575 576 #define mc_set_tsa_passthrough(client) \ 577 { \ 578 mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \ 579 (TSA_CONFIG_STATIC0_CSW_##client##_RESET & \ 580 ~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \ 581 TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \ 582 } 583 584 #define mc_set_forced_coherent_cfg(client) \ 585 { \ 586 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \ 587 MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV); \ 588 } 589 590 #define mc_set_forced_coherent_so_dev_cfg(client) \ 591 { \ 592 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \ 593 MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV | \ 594 MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT); \ 595 } 596 597 #define mc_set_forced_coherent_axid_so_dev_cfg(client) \ 598 { \ 599 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \ 600 MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV | \ 601 MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID | \ 602 MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT); \ 603 } 604 605 #endif /* __MEMCTRLV2_H__ */ 606