1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <bl_common.h> 34 #include <console.h> 35 #include <context.h> 36 #include <context_mgmt.h> 37 #include <cortex_a57.h> 38 #include <debug.h> 39 #include <denver.h> 40 #include <interrupt_mgmt.h> 41 #include <mce.h> 42 #include <platform.h> 43 #include <tegra_def.h> 44 #include <tegra_private.h> 45 #include <xlat_tables.h> 46 47 DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1) 48 extern uint64_t tegra_enable_l2_ecc_parity_prot; 49 50 /******************************************************************************* 51 * The Tegra power domain tree has a single system level power domain i.e. a 52 * single root node. The first entry in the power domain descriptor specifies 53 * the number of power domains at the highest power level. 54 ******************************************************************************* 55 */ 56 const unsigned char tegra_power_domain_tree_desc[] = { 57 /* No of root nodes */ 58 1, 59 /* No of clusters */ 60 PLATFORM_CLUSTER_COUNT, 61 /* No of CPU cores - cluster0 */ 62 PLATFORM_MAX_CPUS_PER_CLUSTER, 63 /* No of CPU cores - cluster1 */ 64 PLATFORM_MAX_CPUS_PER_CLUSTER 65 }; 66 67 /* 68 * Table of regions to map using the MMU. 69 */ 70 static const mmap_region_t tegra_mmap[] = { 71 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 72 MT_DEVICE | MT_RW | MT_SECURE), 73 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ 74 MT_DEVICE | MT_RW | MT_SECURE), 75 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 76 MT_DEVICE | MT_RW | MT_SECURE), 77 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 78 MT_DEVICE | MT_RW | MT_SECURE), 79 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB */ 80 MT_DEVICE | MT_RW | MT_SECURE), 81 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ 82 MT_DEVICE | MT_RW | MT_SECURE), 83 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 84 MT_DEVICE | MT_RW | MT_SECURE), 85 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ 86 MT_DEVICE | MT_RW | MT_SECURE), 87 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ 88 MT_DEVICE | MT_RW | MT_SECURE), 89 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ 90 MT_DEVICE | MT_RW | MT_SECURE), 91 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 92 MT_DEVICE | MT_RW | MT_SECURE), 93 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 94 MT_DEVICE | MT_RW | MT_SECURE), 95 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ 96 MT_DEVICE | MT_RW | MT_SECURE), 97 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 98 MT_DEVICE | MT_RW | MT_SECURE), 99 MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x1000000, /* 64KB */ 100 MT_DEVICE | MT_RW | MT_SECURE), 101 {0} 102 }; 103 104 /******************************************************************************* 105 * Set up the pagetables as per the platform memory map & initialize the MMU 106 ******************************************************************************/ 107 const mmap_region_t *plat_get_mmio_map(void) 108 { 109 /* MMIO space */ 110 return tegra_mmap; 111 } 112 113 /******************************************************************************* 114 * Handler to get the System Counter Frequency 115 ******************************************************************************/ 116 unsigned long long plat_get_syscnt_freq(void) 117 { 118 return 31250000; 119 } 120 121 /******************************************************************************* 122 * Maximum supported UART controllers 123 ******************************************************************************/ 124 #define TEGRA186_MAX_UART_PORTS 7 125 126 /******************************************************************************* 127 * This variable holds the UART port base addresses 128 ******************************************************************************/ 129 static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 130 0, /* undefined - treated as an error case */ 131 TEGRA_UARTA_BASE, 132 TEGRA_UARTB_BASE, 133 TEGRA_UARTC_BASE, 134 TEGRA_UARTD_BASE, 135 TEGRA_UARTE_BASE, 136 TEGRA_UARTF_BASE, 137 TEGRA_UARTG_BASE, 138 }; 139 140 /******************************************************************************* 141 * Retrieve the UART controller base to be used as the console 142 ******************************************************************************/ 143 uint32_t plat_get_console_from_id(int id) 144 { 145 if (id > TEGRA186_MAX_UART_PORTS) 146 return 0; 147 148 return tegra186_uart_addresses[id]; 149 } 150 151 /* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */ 152 #define TEGRA186_VER_A02P 0x1201 153 154 /******************************************************************************* 155 * Handler for early platform setup 156 ******************************************************************************/ 157 void plat_early_platform_setup(void) 158 { 159 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 160 uint32_t chip_minor, chip_major, chip_subrev, val; 161 162 /* sanity check MCE firmware compatibility */ 163 mce_verify_firmware_version(); 164 165 /* 166 * Enable ECC and Parity Protection for Cortex-A57 CPUs 167 * for Tegra A02p SKUs 168 */ 169 if (impl != DENVER_IMPL) { 170 171 /* get the major, minor and sub-version values */ 172 chip_major = (mmio_read_32(TEGRA_MISC_BASE + 173 HARDWARE_REVISION_OFFSET) >> 174 MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK; 175 chip_minor = (mmio_read_32(TEGRA_MISC_BASE + 176 HARDWARE_REVISION_OFFSET) >> 177 MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK; 178 chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) & 179 SUBREVISION_MASK; 180 181 /* prepare chip version number */ 182 val = (chip_major << 12) | (chip_minor << 8) | chip_subrev; 183 184 /* enable L2 ECC for Tegra186 A02P and beyond */ 185 if (val >= TEGRA186_VER_A02P) { 186 187 val = read_l2ctlr_el1(); 188 val |= L2_ECC_PARITY_PROTECTION_BIT; 189 write_l2ctlr_el1(val); 190 191 /* 192 * Set the flag to enable ECC/Parity Protection 193 * when we exit System Suspend or Cluster Powerdn 194 */ 195 tegra_enable_l2_ecc_parity_prot = 1; 196 } 197 } 198 } 199 200 /* Secure IRQs for Tegra186 */ 201 static const irq_sec_cfg_t tegra186_sec_irqs[] = { 202 { 203 TEGRA186_TOP_WDT_IRQ, 204 TEGRA186_SEC_IRQ_TARGET_MASK, 205 INTR_TYPE_EL3, 206 }, 207 { 208 TEGRA186_AON_WDT_IRQ, 209 TEGRA186_SEC_IRQ_TARGET_MASK, 210 INTR_TYPE_EL3, 211 }, 212 }; 213 214 /******************************************************************************* 215 * Initialize the GIC and SGIs 216 ******************************************************************************/ 217 void plat_gic_setup(void) 218 { 219 tegra_gic_setup(tegra186_sec_irqs, 220 sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); 221 222 /* 223 * Initialize the FIQ handler only if the platform supports any 224 * FIQ interrupt sources. 225 */ 226 if (sizeof(tegra186_sec_irqs) > 0) 227 tegra_fiq_handler_setup(); 228 } 229