| ff605ba2 | 03-Jan-2018 |
steven kao <skao@nvidia.com> |
Tegra: bpmp_ipc: support to enable/disable module clocks
This patch adds support to the bpmp_ipc driver to allow clients to
enable/disable clocks to hardware blocks. Currently, the API only
supports
Tegra: bpmp_ipc: support to enable/disable module clocks
This patch adds support to the bpmp_ipc driver to allow clients to
enable/disable clocks to hardware blocks. Currently, the API only
supports SE devices.
Change-Id: I9a361e380c0bcda59f5a92ca51c86a46555b2e90
Signed-off-by: steven kao <skao@nvidia.com>
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| 0887026e | 28-Dec-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: default platform handler for the CPU_STANDBY state
This patch adds a default implementation for the platform specific
CPU standby power handler. Tegra SoCs can override this handler
with thei
Tegra: default platform handler for the CPU_STANDBY state
This patch adds a default implementation for the platform specific
CPU standby power handler. Tegra SoCs can override this handler
with their own implementations.
Change-Id: I91e513842f194b1e2b1defa2d833bb4d9df5f06b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| fc5adf7d | 30-Nov-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: memctrl_v2: remove usage of ENABLE_SMMU_DEVICE config
This patch removes the usage of this platform config, as it is always
enabled by all the supported platforms.
Change-Id: Ie7adb641adeb36
Tegra: memctrl_v2: remove usage of ENABLE_SMMU_DEVICE config
This patch removes the usage of this platform config, as it is always
enabled by all the supported platforms.
Change-Id: Ie7adb641adeb3604b177b6960b797722d60addfa
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 3e1923d9 | 27-Oct-2017 |
Dilan Lee <dilee@nvidia.com> |
Tegra: add 'late' platform setup handler
This patch adds a platform setup handler that gets called after
the MMU is enabled. Platforms wanting to make use of this handler
should declare 'plat_late_p
Tegra: add 'late' platform setup handler
This patch adds a platform setup handler that gets called after
the MMU is enabled. Platforms wanting to make use of this handler
should declare 'plat_late_platform_setup' handler in their platform
files, to override the default weakly defined handler.
Change-Id: Ibc97a2e5a24608ddea856d0bd543a9d5876f604c
Signed-off-by: Dilan Lee <dilee@nvidia.com>
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| dd20f5b3 | 15-Nov-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: spe: shared console for Tegra platforms
There are Tegra platforms which have limited UART ports and so
all the components have to share the console. The SPE helps out
by collecting all the lo
Tegra: spe: shared console for Tegra platforms
There are Tegra platforms which have limited UART ports and so
all the components have to share the console. The SPE helps out
by collecting all the logs in such cases and prints them on the
shared UART port.
This patch adds a driver to communicate with the SPE driver, which
in turn provides the console.
Change-Id: Ie750520b936b8bed0ab1d876f03fc0a3490a85a3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 4cba6985 | 15-Nov-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: console driver compilation from platform makefiles
This patch includes the console driver from individual platform
makefiles and removes it from tegra_common.mk. This allows future
platforms
Tegra: console driver compilation from platform makefiles
This patch includes the console driver from individual platform
makefiles and removes it from tegra_common.mk. This allows future
platforms to include consoles of their choice.
Change-Id: I7506562bfac78421a80fb6782ac8472fbef6cfb0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 2ad1bddc | 08-Nov-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: smmu: change exit criteria for context size calculation
Tegra SoCs currently do not have a SMMU register at address 0xFFFFFFFF.
This patch changes the search criteria, to look for this marker
Tegra: smmu: change exit criteria for context size calculation
Tegra SoCs currently do not have a SMMU register at address 0xFFFFFFFF.
This patch changes the search criteria, to look for this marker, to
calculate the size of the saved context.
Change-Id: I15d91945ecb78267f91c45f37985dbb2327ca3ae
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| c63ec263 | 14-Nov-2017 |
Steven Kao <skao@nvidia.com> |
Tegra: memctrl_v2: platform handler for TZDRAM setup
The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers to
Tegra: memctrl_v2: platform handler for TZDRAM setup
The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers to perform custom steps during TZDRAM setup.
Change-Id: Iee094d6ca189c6dd24f1147003c33c99ff3a953b
Signed-off-by: Steven Kao <skao@nvidia.com>
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| d7be5e2e | 23-Aug-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: bpmp: return error if BPMP init fails
This patch returns error if BPMP initialization fails. The platform
code marks the cluster as "runnning" since we wont be able to get
it into the low pow
Tegra: bpmp: return error if BPMP init fails
This patch returns error if BPMP initialization fails. The platform
code marks the cluster as "runnning" since we wont be able to get
it into the low power state without BPMP.
Change-Id: I86f51d478626240bb7b4ccede8907674290c5dc1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 601a8e54 | 23-Oct-2017 |
Steven Kao <skao@nvidia.com> |
Tegra: rename secure scratch register macros
This patch renames all the secure scratch registers to reflect their
usage.
This is a list of all the macros being renamed:
- SECURE_SCRATCH_RSV1_* ->
Tegra: rename secure scratch register macros
This patch renames all the secure scratch registers to reflect their
usage.
This is a list of all the macros being renamed:
- SECURE_SCRATCH_RSV1_* -> SCRATCH_RESET_VECTOR_*
- SECURE_SCRATCH_RSV6 -> SCRATCH_SECURE_BOOTP_FCFG
- SECURE_SCRATCH_RSV11_* -> SCRATCH_SMMU_TABLE_ADDR_*
- SECURE_SCRATCH_RSV53_* -> SCRATCH_BOOT_PARAMS_ADDR_*
- SECURE_SCRATCH_RSV55_* -> SCRATCH_TZDRAM_ADDR_*
NOTE: Future SoCs will have to define these macros to
keep the drivers functioning.
Change-Id: Ib3ba40dd32e77b92b47825f19c420e6fdfa8b987
Signed-off-by: Steven Kao <skao@nvidia.com>
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| d5bd0de6 | 30-Oct-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: memctrl_v2: platform handler for TZDRAM settings
The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers
Tegra: memctrl_v2: platform handler for TZDRAM settings
The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers to perform platform specific steps, e.g. enable encryption,
save base/size to secure scratch registers.
Change-Id: Ifaa2e0eac20b50f77ec734256544c36dd511bd63
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 26e2b93a | 25-Sep-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: bpmp_ipc: IPC driver to communicate with BPMP firmware
This patch adds the driver to communicate with the BPMP firmware on Tegra
SoCs, starting Tegra186. BPMP firmware is responsible for cloc
Tegra: bpmp_ipc: IPC driver to communicate with BPMP firmware
This patch adds the driver to communicate with the BPMP firmware on Tegra
SoCs, starting Tegra186. BPMP firmware is responsible for clock enable/
disable requests, module resets among other things.
MRQ is short for Message ReQuest. This is the general purpose, multi channel
messaging protocol that is widely used to communicate with BPMP. This is further
divided into a common high level protocol and a peer-specific low level protocol.
The higher level protocol specifies the peer identification, channel definition
and allocation, message structure, message semantics and message dispatch process
whereas the lower level protocol defines actual message transfer implementation
details. Currently, BPMP supports two lower level protocols - Token Mail Operations
(TMO), IVC Mail Operations (IMO).
This driver implements the IMO protocol. IMO is implemented using the IVC (Inter-VM
Communication) protocol which is a lockless, shared memory messaging queue management
protocol.
The IVC peer is expected to perform the following as part of establishing a connection
with BPMP.
1. Initialize the channels with tegra_ivc_init() or its equivalent.
2. Reset the channel with tegra_ivc_channel_reset. The peer should also ensure that
BPMP is notified via the doorbell.
3. Poll until the channel connection is established [tegra_ivc_channel_notified() return
0]. Interrupt BPMP with doorbell each time after tegra_ivc_channel_notified() return
non zero.
The IPC driver currently supports reseting the GPCDMAand XUSB_PADCTL hardware blocks. In
future, more hardware blocks would be supported.
Change-Id: I52a4bd3a853de6c4fa410904b6614ff1c63df364
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 01da3bd2 | 20-Sep-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: call 'early_init' handler earlier during boot
This patch calls the 'early_init' handler earlier during boot. This
allows the platforms using Tegra186 onwards to init the BPMP interface
earlie
Tegra: call 'early_init' handler earlier during boot
This patch calls the 'early_init' handler earlier during boot. This
allows the platforms using Tegra186 onwards to init the BPMP interface
earlier.
Change-Id: I0d540df39de7864ce9051ebe11eca5432c462ebf
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| d6306d14 | 06-Sep-2017 |
Steven Kao <skao@nvidia.com> |
Tegra: memctrl_v2: allow CPU accesses to TZRAM
This patch enables CPU access configuration register to allow
accesses to the TZRAM aperture on chips after Tegra186.
Change-Id: I0898582f8bd6fd35360e
Tegra: memctrl_v2: allow CPU accesses to TZRAM
This patch enables CPU access configuration register to allow
accesses to the TZRAM aperture on chips after Tegra186.
Change-Id: I0898582f8bd6fd35360ecf8ca5cee21fe35f7aab
Signed-off-by: Steven Kao <skao@nvidia.com>
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| 91196b02 | 08-Sep-2017 |
Anthony Zhou <anzhou@nvidia.com> |
Tegra: lib: debug: fix MISRA violation Rule 21.6
MISRA Rule 21.6, The standard library input/output functions
shall not be used.
This patch removes headers that are not really needed.
Change-Id: I
Tegra: lib: debug: fix MISRA violation Rule 21.6
MISRA Rule 21.6, The standard library input/output functions
shall not be used.
This patch removes headers that are not really needed.
Change-Id: I746138ce7ee95d7ca985d020f89b2738d997a7a2
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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| b886c7c5 | 18-Sep-2017 |
Harvey Hsieh <hhsieh@nvidia.com> |
Tegra: memctrl_v2: pack TZDRAM base to RSVD55_SCRATCH
This patch saves the TZDRAM_BASE value to secure RSVD55
scratch register. The warmboot code uses this register to
restore the settings on exitin
Tegra: memctrl_v2: pack TZDRAM base to RSVD55_SCRATCH
This patch saves the TZDRAM_BASE value to secure RSVD55
scratch register. The warmboot code uses this register to
restore the settings on exiting System Suspend.
Change-Id: Id76175c2a7d931227589468511365599e2908411
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
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| ab2eb455 | 04-Aug-2017 |
Puneet Saxena <puneets@nvidia.com> |
Tegra: memctrl_v2: platform handlers to program MSS
Introduce platform handlers to program the MSS settings.
This allows the current driver to scale to future chips.
Change-Id: I40a27648a1a3c73b1ce
Tegra: memctrl_v2: platform handlers to program MSS
Introduce platform handlers to program the MSS settings.
This allows the current driver to scale to future chips.
Change-Id: I40a27648a1a3c73b1ce38dafddc1babb6f0b0d9b
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
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| 650d9c52 | 21-Aug-2017 |
Harvey Hsieh <hhsieh@nvidia.com> |
Tegra: memctrl: clean MC INT status before exit to bootloader
This patch cleans the Memory controller's interrupt status
register, before exiting to the non-secure world during
cold boot. This is re
Tegra: memctrl: clean MC INT status before exit to bootloader
This patch cleans the Memory controller's interrupt status
register, before exiting to the non-secure world during
cold boot. This is required as we observed that the MC's
arbitration bit is set before exiting the secure world.
Change-Id: Iacd01994d03b3b9cbd7b8a57fe7ab5b04e607a9f
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
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| b627d083 | 23-Aug-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: use 'PLATFORM_MAX_CPUS_PER_CLUSTER' to calculate core position
This patch updates the plat_my_core_pos() and platform_get_core_pos() helper
functions to use the `PLATFORM_MAX_CPUS_PER_CLUSTER
Tegra: use 'PLATFORM_MAX_CPUS_PER_CLUSTER' to calculate core position
This patch updates the plat_my_core_pos() and platform_get_core_pos() helper
functions to use the `PLATFORM_MAX_CPUS_PER_CLUSTER` macro to calculate the
core position.
core_pos = CoreId + (ClusterId * PLATFORM_MAX_CPUS_PER_CLUSTER)
Change-Id: Ic49f2fc7ded23bf9484c8fe104025df8884b9faf
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 70da35b0 | 09-Aug-2017 |
Harvey Hsieh <hhsieh@nvidia.com> |
Tegra: memctrl_v2: pack TZDRAM base into SCRATCH54_LO
This patch moves the TZDRAM base address to SCRATCH55_LO due
to security concerns. The HI and LO address bits are packed
into SCRATCH55_LO for t
Tegra: memctrl_v2: pack TZDRAM base into SCRATCH54_LO
This patch moves the TZDRAM base address to SCRATCH55_LO due
to security concerns. The HI and LO address bits are packed
into SCRATCH55_LO for the warmboot firmware to restore.
SCRATCH54_HI is still being used for backward compatibility,
but would be removed eventually.
The scratch registers are populated as:
* RSV55_0 = CFG1[12:0] | CFG0[31:20]
* RSV55_1 = CFG3[1:0]
* RSV54_1 = CFG1[12:0]
Change-Id: Idc20d165d8117488010fcc8dfd946f7ad475da58
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
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| c09c63ee | 15-Jun-2017 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
Tegra: bpmp: Increase timeout to 2ms
To deal with upcoming EMC periodic compensation, increase the BPMP timeout
to 2ms.
Change-Id: I8572c031168defd15504d905c4d625f44dd7fa3d
Signed-off-by: Peter De
Tegra: bpmp: Increase timeout to 2ms
To deal with upcoming EMC periodic compensation, increase the BPMP timeout
to 2ms.
Change-Id: I8572c031168defd15504d905c4d625f44dd7fa3d
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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| a9cbc0cb | 15-Aug-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: remove duplicate code from CPU's power on path
This patch removes duplicate code from the CPU's power on path. The removed
code is already present as part of PSCI's power on logic.
Change-Id
Tegra: remove duplicate code from CPU's power on path
This patch removes duplicate code from the CPU's power on path. The removed
code is already present as part of PSCI's power on logic.
Change-Id: I4d18a605b219570c6bf997b9e6be6e7853ebf5cd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| db82b619 | 03-Jan-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: trusty: pass profiling base to Trusted OS
* Previous boot loader passes Shared DRAM address
to be used by Trusted OS to dump its boot timing records
* This patch adds support to pass the pa
Tegra: trusty: pass profiling base to Trusted OS
* Previous boot loader passes Shared DRAM address
to be used by Trusted OS to dump its boot timing records
* This patch adds support to pass the parameter
to Trusted OS during cold boot
Change-Id: I9f95bb6de80b1bbd2d2d6ec42619f895d911b8ed
Signed-off-by: Akshay Sharan <asharan@nvidia.com>
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| 7a6e0537 | 03-Aug-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: memctrl: assert if dynamic memmap fails
This patch adds an assert in case the dynamic memmap routine fails.
Change-Id: Idd20debbb8944340f5928c6f2cfea973a63a7b1c
Signed-off-by: Varun Wadekar
Tegra: memctrl: assert if dynamic memmap fails
This patch adds an assert in case the dynamic memmap routine fails.
Change-Id: Idd20debbb8944340f5928c6f2cfea973a63a7b1c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 087cf68a | 21-Jul-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: lib: library for profiling the cold boot path
The non secure world would like to profile the boot path for
the EL3 and S-EL1 firmwares. To allow it to do that, a non-secure
DRAM region (4K) i
Tegra: lib: library for profiling the cold boot path
The non secure world would like to profile the boot path for
the EL3 and S-EL1 firmwares. To allow it to do that, a non-secure
DRAM region (4K) is allocated and the base address is passed to
the EL3 firmware.
This patch adds a library to allow the platform code to store the
tag:timestamp pair to the shared memory. The tegra platform code
then uses the `record` method to add timestamps.
Original change by Akshay Sharan <asharan@nvidia.com>
Change-Id: Idbbef9c83ed84a508b04d85a6637775960dc94ba
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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