1# 2# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# platform configs 8ENABLE_AFI_DEVICE := 1 9$(eval $(call add_define,ENABLE_AFI_DEVICE)) 10 11ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 1 12$(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS)) 13 14RELOCATE_TO_BL31_BASE := 1 15$(eval $(call add_define,RELOCATE_TO_BL31_BASE)) 16 17ENABLE_CHIP_VERIFICATION_HARNESS := 0 18$(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS)) 19 20RESET_TO_BL31 := 1 21 22PROGRAMMABLE_RESET_ADDRESS := 1 23 24COLD_BOOT_SINGLE_CPU := 1 25 26# platform settings 27TZDRAM_BASE := 0x30000000 28$(eval $(call add_define,TZDRAM_BASE)) 29 30PLATFORM_CLUSTER_COUNT := 2 31$(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) 32 33PLATFORM_MAX_CPUS_PER_CLUSTER := 4 34$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) 35 36MAX_XLAT_TABLES := 24 37$(eval $(call add_define,MAX_XLAT_TABLES)) 38 39MAX_MMAP_REGIONS := 24 40$(eval $(call add_define,MAX_MMAP_REGIONS)) 41 42# platform files 43PLAT_INCLUDES += -I${SOC_DIR}/drivers/include 44 45BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ 46 lib/cpus/aarch64/denver.S \ 47 lib/cpus/aarch64/cortex_a57.S \ 48 ${COMMON_DIR}/drivers/gpcdma/gpcdma.c \ 49 ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \ 50 ${COMMON_DIR}/drivers/smmu/smmu.c \ 51 ${SOC_DIR}/drivers/mce/mce.c \ 52 ${SOC_DIR}/drivers/mce/ari.c \ 53 ${SOC_DIR}/drivers/mce/nvg.c \ 54 ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \ 55 ${SOC_DIR}/plat_memctrl.c \ 56 ${SOC_DIR}/plat_psci_handlers.c \ 57 ${SOC_DIR}/plat_setup.c \ 58 ${SOC_DIR}/plat_secondary.c \ 59 ${SOC_DIR}/plat_sip_calls.c \ 60 ${SOC_DIR}/plat_smmu.c \ 61 ${SOC_DIR}/plat_trampoline.S 62 63# Enable workarounds for selected Cortex-A57 erratas. 64A57_DISABLE_NON_TEMPORAL_HINT := 1 65ERRATA_A57_806969 := 1 66ERRATA_A57_813419 := 1 67ERRATA_A57_813420 := 1 68ERRATA_A57_826974 := 1 69ERRATA_A57_826977 := 1 70ERRATA_A57_828024 := 1 71ERRATA_A57_829520 := 1 72ERRATA_A57_833471 := 1 73