| f2800a47 | 06-Apr-2021 |
Pali Rohár <pali@kernel.org> |
plat: marvell: armada: a3k: Add new compile option A3720_DB_PM_WAKEUP_SRC
This new compile option is only for Armada 3720 Development Board. When
it is set to 1 then TF-A will setup PM wake up src c
plat: marvell: armada: a3k: Add new compile option A3720_DB_PM_WAKEUP_SRC
This new compile option is only for Armada 3720 Development Board. When
it is set to 1 then TF-A will setup PM wake up src configuration.
By default this new option is disabled as it is board specific and no
other A37xx board has PM wake up src configuration.
Currently neither upstream U-Boot nor upstream Linux kernel has wakeup
support for A37xx platforms, so having it disabled does not cause any
issue.
Prior this commit PM wake up src configuration specific for Armada 3720
Development Board was enabled for every A37xx board. After this change it
is enabled only when compiling with build flag A3720_DB_PM_WAKEUP_SRC=1
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I09fea1172c532df639acb3bb009cfde32d3c5766
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| e3afea43 | 22-Mar-2021 |
Konstantin Porotchkin <kostap@marvell.com> |
plat/marvell: remove subversion from Marvell make files
Subversion is not reflecting the Marvell sources variant anymore.
This patch removes version.mk from Marvell plafroms.
Signed-off-by: Konstan
plat/marvell: remove subversion from Marvell make files
Subversion is not reflecting the Marvell sources variant anymore.
This patch removes version.mk from Marvell plafroms.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: I8f3afbe3fab3a38da68876f77455f449f5fe0179
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| 90eac170 | 07-Mar-2021 |
Konstantin Porotchkin <kostap@marvell.com> |
plat/marvell: a8k: move efuse definitions to separate header
Move efuse definitions to a separate header file for later
usage with other FW modules.
Change-Id: I2e9465f760d0388c8e5863bc64a4cdc57de2
plat/marvell: a8k: move efuse definitions to separate header
Move efuse definitions to a separate header file for later
usage with other FW modules.
Change-Id: I2e9465f760d0388c8e5863bc64a4cdc57de2417f
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/47313
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Yi Guo <yi.guo@cavium.com>
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| 2e1dba44 | 02-Aug-2020 |
Konstantin Porotchkin <kostap@marvell.com> |
plat/marvell/armada: fix TRNG return SMC handling
Use single 64b register for the return value instead of two 32b.
Report an error if caller requested larger than than 64b random
number in a single
plat/marvell/armada: fix TRNG return SMC handling
Use single 64b register for the return value instead of two 32b.
Report an error if caller requested larger than than 64b random
number in a single SMC call.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Ib8756cd3c0808b78c359f90c6f6913f7d16ac360
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/33280
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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| 550a06df | 24-Jun-2020 |
Alex Evraev <alexev@marvell.com> |
drivers: marvell: comphy: add rx training on 10G port
This patch forces rx training on 10G ports
as part of comphy_smc call from Linux.
Signed-off-by: Alex Evraev <alexev@marvell.com>
Change-Id: Ie
drivers: marvell: comphy: add rx training on 10G port
This patch forces rx training on 10G ports
as part of comphy_smc call from Linux.
Signed-off-by: Alex Evraev <alexev@marvell.com>
Change-Id: Iebe6ea7c8b21cbdce5c466c8a69b92e9d7c8a8ca
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30763
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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| b5a06637 | 28-Feb-2021 |
Konstantin Porotchkin <kostap@marvell.com> |
plat/marvell/armada: postpone MSS CPU startup to BL31 stage
Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2.
However, (especailly in secure boot mode), some bus attributes s
plat/marvell/armada: postpone MSS CPU startup to BL31 stage
Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2.
However, (especailly in secure boot mode), some bus attributes should be
changed from defaults before the MSS CPU tries to access shared resources.
This patch starts to use CP MSS SRAM for FW load in both secure and
non-secure boot modes.
The FW loader inserts a magic number into MSS SRAM as an indicator of
successfully loaded FS during the BL2 stage and skips releasing the MSS
CPU from the reset state.
Then, at BL31 stage, the MSS CPU is released from reset following the
call to cp110_init function that handles all the required bus attributes
configurations.
Change-Id: Idcf81cc350a086835abed365154051dd79f1ce2e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46890
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
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| ed1587d0 | 17-Feb-2021 |
Guo Yi <yguo@cavium.com> |
plat: marvell: armada: a8k: Fix LD selector mask
Fixed a bug that the actually bit number was used as a mask to
select LD0 or LD1 fuse
Signed-off-by: Guo Yi <yguo@cavium.com>
Change-Id: I4bec268c3d
plat: marvell: armada: a8k: Fix LD selector mask
Fixed a bug that the actually bit number was used as a mask to
select LD0 or LD1 fuse
Signed-off-by: Guo Yi <yguo@cavium.com>
Change-Id: I4bec268c3dc2566350b4a73f655bce222707e25b
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46146
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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| 718dbcac | 12-Oct-2020 |
Konstantin Porotchkin <kostap@marvell.com> |
plat/marvell/armada: allow builds without MSS support
Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2
definition.
Images build with MSS_SUPPORT=0 will not include service CPUs
FW and w
plat/marvell/armada: allow builds without MSS support
Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2
definition.
Images build with MSS_SUPPORT=0 will not include service CPUs
FW and will not support PM, FC and other features implemented
in these FW images.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Idf301ebd218ce65a60f277f3876d0aeb6c72f105
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/37769
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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| 81c2a044 | 03-Jan-2020 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
drivers: marvell: add support for secure read/write of dfx register-set
Since the dfx register set is going to be marked as secure expose dfx
secure read and write function via SiP services. In intr
drivers: marvell: add support for secure read/write of dfx register-set
Since the dfx register set is going to be marked as secure expose dfx
secure read and write function via SiP services. In introduced misc_dfx
driver some registers are white-listed so non-secure software can still
access them.
This will allow non-secure word drivers access some white-listed
registers related to e.g.: Sample at reset, efuses, SoC type and
revision ID accesses.
Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25055
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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| b81444e8 | 25-Dec-2019 |
Alex Leibovich <alexl@marvell.com> |
ddr_phy: use smc calls to access ddr phy registers
Added smc calls support to access ddr phy registers.
Change-Id: Ibaa0a8e20b6398ab394c7e2e9ea61f9a28cdb870
Signed-off-by: Alex Leibovich <alexl@mar
ddr_phy: use smc calls to access ddr phy registers
Added smc calls support to access ddr phy registers.
Change-Id: Ibaa0a8e20b6398ab394c7e2e9ea61f9a28cdb870
Signed-off-by: Alex Leibovich <alexl@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/20791
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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| 0cedca63 | 02-Jan-2020 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
drivers: marvell: thermal: use dedicated function for thermal SiPs
Since more drivers which uses dfx register set need to be handled with
use of SiP services, use dedicated and more meaningful name
drivers: marvell: thermal: use dedicated function for thermal SiPs
Since more drivers which uses dfx register set need to be handled with
use of SiP services, use dedicated and more meaningful name for thermal
SiP services.
Change-Id: Ic2ac27535a4902477df8edc4c86df3e34cb2344f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25054
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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| ad416958 | 18-Dec-2019 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
drivers: marvell: add thermal sensor driver and expose it via SIP service
Since the dfx register set is going to be marked as secure (in order to
protect efuse registers for non secure access), acce
drivers: marvell: add thermal sensor driver and expose it via SIP service
Since the dfx register set is going to be marked as secure (in order to
protect efuse registers for non secure access), accessing thermal
registers which are part of dfx register set, will not be possible from
lower exception levels. Due to above expose thermal driver as a SiP
service. This will allow Linux and U-Boot thermal driver to initialise
and perform various operations on thermal sensor.
The thermal sensor driver is based on Linux
drivers/thermal/armada_thermal.c.
Change-Id: I4763a3bf5c43750c724c86b1dcadad3cb729e93e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/20581
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>
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| dceac436 | 22-Mar-2021 |
Konstantin Porotchkin <kostap@marvell.com> |
fix: plat: marvell: fix MSS loader for A8K family
Wrong brakets caused MSS FW load timeout error:
ERROR: MSS DMA failed (timeout)
ERROR: MSS FW chunk 0 load failed
ERROR: SCP Image load failed
fix: plat: marvell: fix MSS loader for A8K family
Wrong brakets caused MSS FW load timeout error:
ERROR: MSS DMA failed (timeout)
ERROR: MSS FW chunk 0 load failed
ERROR: SCP Image load failed
This patch fixes the operator precedence in MSS FW load.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: I78c215606bde112f40429926c51f5fa1e4334c13
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| 5a9f5890 | 17-Jun-2020 |
Konstantin Porotchkin <kostap@marvell.com> |
plat/marvell/armada: cleanup MSS SRAM if used for copy
This patch cleans up the MSS SRAM if it was used for MSS image
copy (secure boot mode).
Change-Id: I23f600b512050f75e63d59541b9c21cef21ed313
S
plat/marvell/armada: cleanup MSS SRAM if used for copy
This patch cleans up the MSS SRAM if it was used for MSS image
copy (secure boot mode).
Change-Id: I23f600b512050f75e63d59541b9c21cef21ed313
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30099
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
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| 109873cf | 29-Sep-2020 |
Konstantin Porotchkin <kostap@marvell.com> |
plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage
Map IO WIN to CP1 and CP2 at all stages including the BLE.
Do not map CP1/CP2 if CP_NUM is lower than 2 and 3 accordingly.
This patch allows
plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage
Map IO WIN to CP1 and CP2 at all stages including the BLE.
Do not map CP1/CP2 if CP_NUM is lower than 2 and 3 accordingly.
This patch allows access to CP1/CP2 internal registers at
BLE stage if CP1/CP2 are connected.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Icf9ffdf2e9e3cdc2a153429ffd914cc0005f9eca
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/36939
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Yi Guo <yi.guo@cavium.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
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| 57870747 | 29-Jan-2020 |
Konstantin Porotchkin <kostap@marvell.com> |
plat/marvell/armada/common/mss: use MSS SRAM in secure mode
The CP MSS IRAM is only accessible by CM3 CPU and MSS DMA.
In secure boot mode the MSS DMA is unable to directly load
the MSS FW image fro
plat/marvell/armada/common/mss: use MSS SRAM in secure mode
The CP MSS IRAM is only accessible by CM3 CPU and MSS DMA.
In secure boot mode the MSS DMA is unable to directly load
the MSS FW image from DRAM to IRAM.
This patch adds support for using the MSS SRAM as intermediate
storage. The MSS FW image is loaded by application CPU into the
MSS SRAM first, then transferred to MSS IRAM by MSS DMA.
Such change allows the CP MSS image load in secure mode.
Change-Id: Iee7a51d157743a0bdf8acb668ee3d599f760a712
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaszczyk@marvell.com>
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| 1e179c79 | 03-Mar-2020 |
Konstantin Porotchkin <kostap@marvell.com> |
plat/marvell: fix SPD handling in dram port
The DRAM port code issues a dummy write to SPD page-0 i2c address
in order to select this page for the forthcoming read transaction.
If the write buffer l
plat/marvell: fix SPD handling in dram port
The DRAM port code issues a dummy write to SPD page-0 i2c address
in order to select this page for the forthcoming read transaction.
If the write buffer length supplied to i2c_write is not zero, this
call is translated to 2 bus transations:
- set the target offset
- write the data to the target
However no actual data should be transferred to SPD page-0 in order
to select it. Actually, the second transation never receives an ACK
from the target device, which caused the following error report:
ERROR: Status 30 in write transaction
This patch sets the buffer length in page-0 select writes to zero,
leading to bypass the data transfer to the target device.
Issuing the target offset command to SPD page-0 address effectively
selects this page for the read operation.
Change-Id: I4bf8e8c09da115ee875f934bc8fbc9349b995017
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/24387
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Moti Buskila <motib@marvell.com>
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| 57660d9d | 26-Jul-2020 |
Konstantin Porotchkin <kostap@marvell.com> |
plat/marvell/armada/a8k: support HW RNG by SMC
Add initialization for TRNG-IP-76 driver and support SMC call
0xC200FF11 used for reading HW RNG value by secondary bootloader
software for KASLR suppo
plat/marvell/armada/a8k: support HW RNG by SMC
Add initialization for TRNG-IP-76 driver and support SMC call
0xC200FF11 used for reading HW RNG value by secondary bootloader
software for KASLR support.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: I1d644f67457b28d347523f8a7bfc4eacc45cba68
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/32688
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
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| e01658ea | 29-Jan-2021 |
Pali Rohár <pali@kernel.org> |
plat: marvell: armada: a3k: Do not use 'echo -e' in Makefile
It does not have to be supported by the current shell used in Makefile.
Replace it by a simple echo with implicit newline.
Signed-off-by
plat: marvell: armada: a3k: Do not use 'echo -e' in Makefile
It does not have to be supported by the current shell used in Makefile.
Replace it by a simple echo with implicit newline.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I97fe44986ac36d3079d5258c67f0c9184537e7f0
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| 4e80d151 | 26-Jan-2021 |
Pali Rohár <pali@kernel.org> |
plat: marvell: armada: a3k: Remove unused variable WTMI_SYSINIT_IMG from Makefile
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I322c8aa65437abb61385f58b700a06b3e2e22e4f |
| 07924f82 | 26-Jan-2021 |
Pali Rohár <pali@kernel.org> |
plat: marvell: armada: Show informative build messages and blank lines
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ibc15db07c581eca29c1b1fbfb145cee50dc42605 |
| c0f60e78 | 26-Jan-2021 |
Pali Rohár <pali@kernel.org> |
plat: marvell: armada: Move definition of mrvl_flash target to common marvell_common.mk file
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: If545b3812787cc97b95dbd61ed51c37d30c5d412 |
| 907f8fc1 | 26-Jan-2021 |
Pali Rohár <pali@kernel.org> |
plat: marvell: armada: a3k: Use $(Q) instead of @
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I09fd734510ec7019505263ff0ea381fab36944fa |
| 8b920973 | 26-Jan-2021 |
Pali Rohár <pali@kernel.org> |
plat: marvell: armada: a3k: Add a new target mrvl_uart which builds UART image
This change separates building of flash and UART images, so it is possible
to build only one of these images. Also this
plat: marvell: armada: a3k: Add a new target mrvl_uart which builds UART image
This change separates building of flash and UART images, so it is possible
to build only one of these images. Also this change allows make to build
them in parallel.
Target mrvl_flash now builds only flash image and mrvl_uart only UART
image. This change reflects it also in the documentation.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ie9ce4538d52188dd26d99dfeeb5ad171a5b818f3
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| 57987415 | 26-Jan-2021 |
Pali Rohár <pali@kernel.org> |
plat: marvell: armada: a3k: Build UART image files directly in $(BUILD_UART) subdirectory
This removes need to move files and also allows to build uart and flash
images in parallel.
Signed-off-by:
plat: marvell: armada: a3k: Build UART image files directly in $(BUILD_UART) subdirectory
This removes need to move files and also allows to build uart and flash
images in parallel.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I13bea547d7849615e1c1e11d333c8c99e568d3f6
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