| ad416958 | 18-Dec-2019 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
drivers: marvell: add thermal sensor driver and expose it via SIP service
Since the dfx register set is going to be marked as secure (in order to
protect efuse registers for non secure access), acce
drivers: marvell: add thermal sensor driver and expose it via SIP service
Since the dfx register set is going to be marked as secure (in order to
protect efuse registers for non secure access), accessing thermal
registers which are part of dfx register set, will not be possible from
lower exception levels. Due to above expose thermal driver as a SiP
service. This will allow Linux and U-Boot thermal driver to initialise
and perform various operations on thermal sensor.
The thermal sensor driver is based on Linux
drivers/thermal/armada_thermal.c.
Change-Id: I4763a3bf5c43750c724c86b1dcadad3cb729e93e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/20581
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>
show more ...
|
| 109873cf | 29-Sep-2020 |
Konstantin Porotchkin <kostap@marvell.com> |
plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage
Map IO WIN to CP1 and CP2 at all stages including the BLE.
Do not map CP1/CP2 if CP_NUM is lower than 2 and 3 accordingly.
This patch allows
plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage
Map IO WIN to CP1 and CP2 at all stages including the BLE.
Do not map CP1/CP2 if CP_NUM is lower than 2 and 3 accordingly.
This patch allows access to CP1/CP2 internal registers at
BLE stage if CP1/CP2 are connected.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Icf9ffdf2e9e3cdc2a153429ffd914cc0005f9eca
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/36939
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Yi Guo <yi.guo@cavium.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
show more ...
|
| 57870747 | 29-Jan-2020 |
Konstantin Porotchkin <kostap@marvell.com> |
plat/marvell/armada/common/mss: use MSS SRAM in secure mode
The CP MSS IRAM is only accessible by CM3 CPU and MSS DMA.
In secure boot mode the MSS DMA is unable to directly load
the MSS FW image fro
plat/marvell/armada/common/mss: use MSS SRAM in secure mode
The CP MSS IRAM is only accessible by CM3 CPU and MSS DMA.
In secure boot mode the MSS DMA is unable to directly load
the MSS FW image from DRAM to IRAM.
This patch adds support for using the MSS SRAM as intermediate
storage. The MSS FW image is loaded by application CPU into the
MSS SRAM first, then transferred to MSS IRAM by MSS DMA.
Such change allows the CP MSS image load in secure mode.
Change-Id: Iee7a51d157743a0bdf8acb668ee3d599f760a712
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaszczyk@marvell.com>
show more ...
|
| 57660d9d | 26-Jul-2020 |
Konstantin Porotchkin <kostap@marvell.com> |
plat/marvell/armada/a8k: support HW RNG by SMC
Add initialization for TRNG-IP-76 driver and support SMC call
0xC200FF11 used for reading HW RNG value by secondary bootloader
software for KASLR suppo
plat/marvell/armada/a8k: support HW RNG by SMC
Add initialization for TRNG-IP-76 driver and support SMC call
0xC200FF11 used for reading HW RNG value by secondary bootloader
software for KASLR support.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: I1d644f67457b28d347523f8a7bfc4eacc45cba68
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/32688
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
show more ...
|
| 07924f82 | 26-Jan-2021 |
Pali Rohár <pali@kernel.org> |
plat: marvell: armada: Show informative build messages and blank lines
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ibc15db07c581eca29c1b1fbfb145cee50dc42605 |
| c0f60e78 | 26-Jan-2021 |
Pali Rohár <pali@kernel.org> |
plat: marvell: armada: Move definition of mrvl_flash target to common marvell_common.mk file
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: If545b3812787cc97b95dbd61ed51c37d30c5d412 |
| a9812206 | 24-Nov-2020 |
Pali Rohár <pali@kernel.org> |
Makefile: Do not mark file targets as .PHONY target
Only non-file targets should be set a .PHONY. Otherwise if file target is
set as .PHONY then targets which depends on those file .PHONY targets wo
Makefile: Do not mark file targets as .PHONY target
Only non-file targets should be set a .PHONY. Otherwise if file target is
set as .PHONY then targets which depends on those file .PHONY targets would
be always rebuilt even when their prerequisites are not changed.
File target which needs to be always rebuilt can be specified in Make
system via having a prerequisite on some .PHONY target, instead of marking
whole target as .PHONY. In Makefile projects it is common to create empty
.PHONY target named FORCE for this purpose.
This patch changes all file targets which are set as .PHONY to depends on
new .PHONY target FORCE, to ensure that these file targets are always
rebuilt (as before). Basically they are those targets which calls external
make subprocess.
After FORCE target is specified in main Makefile, remove it from other
Makefile files to prevent duplicate definitions.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iee3b4e0de93879b95eb29a1745a041538412e69e
show more ...
|
| e4bbd39c | 23-Nov-2020 |
Pali Rohár <pali@kernel.org> |
plat: marvell: armada: Add missing FORCE, .PHONY and clean targets
FORCE target is used as a dependency for other file targets which needs to
be always rebuilt. .PHONY target is standard Makefile ta
plat: marvell: armada: Add missing FORCE, .PHONY and clean targets
FORCE target is used as a dependency for other file targets which needs to
be always rebuilt. .PHONY target is standard Makefile target which specify
non-file targets and therefore needs to be always rebuilt.
Targets clean, realclean and distclean are .PHONY targets used to remove
built files. Correctly set that mrvl_clean target is prerequisite for these
clean targets to ensure that built files are removed.
Finally this change with usage of FORCE target allows to remove mrvl_clean
hack from the prerequisites of a8k ${DOIMAGETOOL} target which was used
just to ensure that ${DOIMAGETOOL} is always rebuilt via make subprocess.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2fa8971244b43f101d846fc433ef7b0b6f139c92
show more ...
|
| 91bc2da7 | 29-Oct-2020 |
Pali Rohár <pali@kernel.org> |
plat: marvell: armada: Add new target mrvl_bootimage
This new target builds boot-image.bin binary as described in documentation.
This image does not contain WTMI image and therefore WTP repository i
plat: marvell: armada: Add new target mrvl_bootimage
This new target builds boot-image.bin binary as described in documentation.
This image does not contain WTMI image and therefore WTP repository is not
required for building.
Having ability to build just this boot-image.bin binary without full
flash-image.bin is useful for A3720 Turris MOX board which does not use
Marvell's WTP and a3700_utils.
To reduce duplicity between a8k and a3k code, define this new target and
also definitions for $(BUILD_PLAT)/$(BOOT_IMAGE) in common include file
marvell_common.mk.
For this purpose it is needed to include plat/marvell/marvell.mk file from
a3700_common.mk unconditionally (and not only when WTP is defined). Now
when common file plat/marvell/marvell.mk does not contain definition for
building $(DOIMAGETOOL), it is possible to move its inclusion at the top of
the a3700_common.mk file.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ic58303b37a1601be9a06ff83b7a279cb7cfc8280
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|
| b5e3d540 | 21-Oct-2020 |
Pali Rohár <pali@kernel.org> |
plat: marvell: armada: Building ${DOIMAGETOOL} is only for a8k
Currently a3k target is misusing ${DOIMAGETOOL} target for building flash
and UART images. It is not used for building image tool.
So
plat: marvell: armada: Building ${DOIMAGETOOL} is only for a8k
Currently a3k target is misusing ${DOIMAGETOOL} target for building flash
and UART images. It is not used for building image tool.
So move ${DOIMAGETOOL} target from common marvell include file into a8k
include file and add correct invocation of ${MAKE} into a3k for building
flash and UART images.
Part of this change is also checks that MV_DDR_PATH for a3k was specified
by user as this option is required for building a3k flash and UART images.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5ae9d08b8505460933f17836c9b6435fd6e51bb6
show more ...
|
| 0412b732 | 19-Oct-2020 |
Pali Rohár <pali@kernel.org> |
plat: marvell: armada: Fix including plat/marvell/marvell.mk file
Include file plat/marvell/marvell.mk for platform A3700 was included two
times. Once from file plat/marvell/armada/a3k/common/a3700_
plat: marvell: armada: Fix including plat/marvell/marvell.mk file
Include file plat/marvell/marvell.mk for platform A3700 was included two
times. Once from file plat/marvell/armada/a3k/common/a3700_common.mk and
second time from common file plat/marvell/armada/common/marvell_common.mk.
It caused following warning every time was make called:
plat/marvell/marvell.mk:51: warning: overriding recipe for target 'mrvl_clean'
plat/marvell/marvell.mk:51: warning: ignoring old recipe for target 'mrvl_clean'
Change in this commit removes inclusion of plat/marvell/marvell.mk file in
common file plat/marvell/armada/common/marvell_common.mk. As a80x0 platform
needs this include file, add it also into a80x0 platform specific include
file lat/marvell/armada/a8k/common/a8k_common.mk.
Also moves inclusion of plat/marvell/marvell.mk file in a3700 platform file
plat/marvell/armada/a3k/common/a3700_common.mk at correct place. Global
plat/marvell/marvell.mk expects that variables DOIMAGEPATH and DOIMAGETOOL
are already defined, but it defines MARVELL_SECURE_BOOT variable which is
needed by plat/marvell/armada/a3k/common/a3700_common.mk.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5cbbd7eb8a3376924419f9850516b2a4924be5aa
show more ...
|
| 6792ba15 | 24-Jun-2019 |
Stefan Chulski <stefanc@marvell.com> |
plat: marvell: ap806: implement workaround for errata-id FE-4265711
ERRATA ID: FE-4265711 - Incorrect CNTVAL reading
CNTVAL reflects the global system counter value in binary format.
Due to this er
plat: marvell: ap806: implement workaround for errata-id FE-4265711
ERRATA ID: FE-4265711 - Incorrect CNTVAL reading
CNTVAL reflects the global system counter value in binary format.
Due to this erratum, the CNTVAL value presented to the processor
may be incorrect for several clock cycles.
Workaround: Override the default value of AP Register Device General
control 20 [19:16] and AP Register Device General Control 21 [11:8]
to the value of 0x3.
Change-Id: I1705608d08acd9631ab98d6f7ceada34d6b8336f
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
show more ...
|
| 8f09da46 | 10-Aug-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "release/14.0" into integration
* changes:
docs: marvell: update PHY porting layer description
docs: marvell: update path in marvell documentation
docs: marvell: updat
Merge changes from topic "release/14.0" into integration
* changes:
docs: marvell: update PHY porting layer description
docs: marvell: update path in marvell documentation
docs: marvell: update build instructions with CN913x
plat: marvell: octeontx: add support for t9130
plat: marvell: t9130: add SVC support
plat: marvell: t9130: update AVS settings
plat: marvell: t9130: pass actual CP count for load_image
plat: marvell: armada: a7k: add support to SVC validation mode
plat: marvell: armada: add support for twin-die combined memory device
show more ...
|
| 29214e95 | 30-Jul-2020 |
Grant Likely <grant.likely@arm.com> |
Use abspath to dereference $BUILD_BASE
If the user tries to change BUILD_BASE to put the build products outside
the build tree the compile will fail due to hard coded assumptions that
$BUILD_BASE is
Use abspath to dereference $BUILD_BASE
If the user tries to change BUILD_BASE to put the build products outside
the build tree the compile will fail due to hard coded assumptions that
$BUILD_BASE is a relative path. Fix by using $(abspath $(BUILD_BASE))
to rationalize to an absolute path every time and remove the relative
path assumptions.
This patch also adds documentation that BUILD_BASE can be specified by
the user.
Signed-off-by: Grant Likely <grant.likely@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib1af874de658484aaffc672f30029b852d2489c8
show more ...
|
| 12c66c6b | 06-May-2019 |
Alex Evraev <alexev@marvell.com> |
plat: marvell: t9130: add SVC support
As the preparation for adding the CN913x SoC family support
introduce code that enable SVC and the frequency handling
specific for the AP807 North Bridge.
Chan
plat: marvell: t9130: add SVC support
As the preparation for adding the CN913x SoC family support
introduce code that enable SVC and the frequency handling
specific for the AP807 North Bridge.
Change-Id: Ibe34a511b49cd9671a2e53b77bdcfc644bb915e3
Signed-off-by: Alex Evraev <alexev@marvell.com>
show more ...
|
| 885cd821 | 24-Jan-2019 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
plat: marvell: t9130: update AVS settings
Update AVS settings and remove unused macros.
This is a preparation patch for adding CN913x SoC
family support.
Change-Id: Ib1dd70885a316ed5763d0f4730d0e47
plat: marvell: t9130: update AVS settings
Update AVS settings and remove unused macros.
This is a preparation patch for adding CN913x SoC
family support.
Change-Id: Ib1dd70885a316ed5763d0f4730d0e4734da117b7
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
show more ...
|
| 5bc3643e | 27-Mar-2019 |
Ben Peled <bpeled@marvell.com> |
plat: marvell: t9130: pass actual CP count for load_image
Add CN913x case to bl2_plat_get_cp_count.
Fix loading of cp1/2 image. This is a preparation
patch for adding CN913x SoC family support.
Cha
plat: marvell: t9130: pass actual CP count for load_image
Add CN913x case to bl2_plat_get_cp_count.
Fix loading of cp1/2 image. This is a preparation
patch for adding CN913x SoC family support.
Change-Id: Id84a30203d20572fc0dfd3f91ea395c199a85fe9
Signed-off-by: Ben Peled <bpeled@marvell.com>
show more ...
|
| ebf307bf | 11-Aug-2019 |
Alex Evraev <alexev@marvell.com> |
plat: marvell: armada: a7k: add support to SVC validation mode
Add support for “AVS reduction” feature at this mode for
7040 Dual Cluster operation mode at CPU=1600MHz
Change-Id: Ia72b10e0ccfad0756
plat: marvell: armada: a7k: add support to SVC validation mode
Add support for “AVS reduction” feature at this mode for
7040 Dual Cluster operation mode at CPU=1600MHz
Change-Id: Ia72b10e0ccfad07568bf4c089ea3990173ae24b2
Signed-off-by: Alex Evraev <alexev@marvell.com>
show more ...
|
| 07678ff7 | 21-Jul-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I0826ef8b,I9b4659a1 into integration
* changes:
plat: marvell: armada: a8k: Add support for iEi Puzzle-M801 board
plat: marvell: armada: a8k: common: Fix a8k_common.mk to use BOARD
Merge changes I0826ef8b,I9b4659a1 into integration
* changes:
plat: marvell: armada: a8k: Add support for iEi Puzzle-M801 board
plat: marvell: armada: a8k: common: Fix a8k_common.mk to use BOARD_DIR variable
show more ...
|
| 0a977b9b | 15-Apr-2019 |
Konstantin Porotchkin <kostap@marvell.com> |
plat: marvell: armada: a8k: change CCU LLC SRAM mapping
The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage.
The CCU have to prepare SRAM window, but point to the DRAM-0 target
unt
plat: marvell: armada: a8k: change CCU LLC SRAM mapping
The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage.
The CCU have to prepare SRAM window, but point to the DRAM-0 target
until the SRAM is actually enabled.
This patch changes CCU SRAM window target to DRAM-0
Remove dependence between LLC_SRAM and LLC_ENABLE and update the
build documentation.
The SRAМ base moved to follow the OP-TEE SHMEM area (0x05400000)
Change-Id: I85c2434a3d515ec37da5ae8eb729e3280f91c456
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
show more ...
|
| 0eb3d1fc | 15-Apr-2019 |
Konstantin Porotchkin <kostap@marvell.com> |
plat: marvell: armada: adjust trusted DRAM size to match OP-TEE OS
Area used as trusted DRAM is 12MB in Marvell OP-TEE OS module.
It is followed by 4MB of shared memory.
Change-Id: If8edeeec5861b52
plat: marvell: armada: adjust trusted DRAM size to match OP-TEE OS
Area used as trusted DRAM is 12MB in Marvell OP-TEE OS module.
It is followed by 4MB of shared memory.
Change-Id: If8edeeec5861b529408baca25f78c06a0a440d8c
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
show more ...
|
| 9b883673 | 12-Apr-2019 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
drivers: marvell: mg_conf_cm3: add basic driver
Implement function which will allow to start AP FW.
Change-Id: Ie0fc8ad138bf56b10809cdc92d1e5e96a2aaf33f
Signed-off-by: Grzegorz Jaszczyk <jaz@semiha
drivers: marvell: mg_conf_cm3: add basic driver
Implement function which will allow to start AP FW.
Change-Id: Ie0fc8ad138bf56b10809cdc92d1e5e96a2aaf33f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
show more ...
|
| 148798cd | 03-Jul-2020 |
Luka Kovacic <luka.kovacic@sartura.hr> |
plat: marvell: armada: a8k: common: Fix a8k_common.mk to use BOARD_DIR variable
Use the BOARD_DIR variable instead of PLAT_FAMILY_BASE variable for
determening the path of the system_power.c file.
plat: marvell: armada: a8k: common: Fix a8k_common.mk to use BOARD_DIR variable
Use the BOARD_DIR variable instead of PLAT_FAMILY_BASE variable for
determening the path of the system_power.c file.
The variable was not updated, when it was deprecated in a8k_common.mk
in commit 613bbde09e48874658af5a00612fe2a0b0388523.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Change-Id: I9b4659a19ba3cd5c869d44c5d834b220f49136e8
show more ...
|
| 47d1773f | 15-Apr-2019 |
Konstantin Porotchkin <kostap@marvell.com> |
plat: marvell: armada: a8k: add OP-TEE OS MMU tables
Adjust the latest OP-TEE memory definitions to the
newest TF-A baseline.
Change-Id: Ib9c82b85f868adaf3c7285eb340486bda9c59c36
Signed-off-by: Kon
plat: marvell: armada: a8k: add OP-TEE OS MMU tables
Adjust the latest OP-TEE memory definitions to the
newest TF-A baseline.
Change-Id: Ib9c82b85f868adaf3c7285eb340486bda9c59c36
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
show more ...
|
| 94d6f483 | 19-Jun-2020 |
Marcin Wojtas <mw@semihalf.com> |
plat: marvell: armada: reduce memory size reserved for FIP image
It is not needed to reserve 64MB for FIP. Limit this to 4MB
for both supported Armada SoC families.
Change-Id: I58a8ce4408a646fe1afd
plat: marvell: armada: reduce memory size reserved for FIP image
It is not needed to reserve 64MB for FIP. Limit this to 4MB
for both supported Armada SoC families.
Change-Id: I58a8ce4408a646fe1afd3c1ea1ed54007c8d205d
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
[Extract from bigger commit]
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
show more ...
|