1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <common/debug.h> 9 #include <drivers/marvell/ap807_clocks_init.h> 10 #include <drivers/marvell/aro.h> 11 #include <drivers/marvell/ccu.h> 12 #include <drivers/marvell/io_win.h> 13 #include <drivers/marvell/mochi/ap_setup.h> 14 #include <drivers/marvell/mochi/cp110_setup.h> 15 16 #include <armada_common.h> 17 #include <mv_ddr_if.h> 18 #include <mvebu_def.h> 19 #include <plat_marvell.h> 20 21 /* Register for skip image use */ 22 #define SCRATCH_PAD_REG2 0xF06F00A8 23 #define SCRATCH_PAD_SKIP_VAL 0x01 24 #define NUM_OF_GPIO_PER_REG 32 25 26 #define MMAP_SAVE_AND_CONFIG 0 27 #define MMAP_RESTORE_SAVED 1 28 29 /* SAR clock settings */ 30 #define MVEBU_AP_GEN_MGMT_BASE (MVEBU_RFU_BASE + 0x8000) 31 #define MVEBU_AP_SAR_REG_BASE(r) (MVEBU_AP_GEN_MGMT_BASE + 0x200 +\ 32 ((r) << 2)) 33 34 #define SAR_CLOCK_FREQ_MODE_OFFSET (0) 35 #define SAR_CLOCK_FREQ_MODE_MASK (0x1f << SAR_CLOCK_FREQ_MODE_OFFSET) 36 #define SAR_PIDI_LOW_SPEED_OFFSET (20) 37 #define SAR_PIDI_LOW_SPEED_MASK (1 << SAR_PIDI_LOW_SPEED_OFFSET) 38 #define SAR_PIDI_LOW_SPEED_SHIFT (15) 39 #define SAR_PIDI_LOW_SPEED_SET (1 << SAR_PIDI_LOW_SPEED_SHIFT) 40 41 #define FREQ_MODE_AP_SAR_REG_NUM (0) 42 #define SAR_CLOCK_FREQ_MODE(v) (((v) & SAR_CLOCK_FREQ_MODE_MASK) >> \ 43 SAR_CLOCK_FREQ_MODE_OFFSET) 44 45 #define AVS_I2C_EEPROM_ADDR 0x57 /* EEPROM */ 46 #define AVS_EN_CTRL_REG (MVEBU_AP_GEN_MGMT_BASE + 0x130) 47 #define AVS_ENABLE_OFFSET (0) 48 #define AVS_SOFT_RESET_OFFSET (2) 49 #define AVS_TARGET_DELTA_OFFSET (21) 50 51 #ifndef MVEBU_SOC_AP807 52 /* AP806 SVC bits */ 53 #define AVS_LOW_VDD_LIMIT_OFFSET (4) 54 #define AVS_HIGH_VDD_LIMIT_OFFSET (12) 55 #define AVS_VDD_LOW_LIMIT_MASK (0xFF << AVS_LOW_VDD_LIMIT_OFFSET) 56 #define AVS_VDD_HIGH_LIMIT_MASK (0xFF << AVS_HIGH_VDD_LIMIT_OFFSET) 57 #else 58 /* AP807 SVC bits */ 59 #define AVS_LOW_VDD_LIMIT_OFFSET (3) 60 #define AVS_HIGH_VDD_LIMIT_OFFSET (13) 61 #define AVS_VDD_LOW_LIMIT_MASK (0x3FF << AVS_LOW_VDD_LIMIT_OFFSET) 62 #define AVS_VDD_HIGH_LIMIT_MASK (0x3FF << AVS_HIGH_VDD_LIMIT_OFFSET) 63 #endif 64 65 /* VDD limit is 0.9V for A70x0 @ CPU frequency < 1600MHz */ 66 #define AVS_A7K_LOW_CLK_VALUE ((0x80 << AVS_TARGET_DELTA_OFFSET) | \ 67 (0x1A << AVS_HIGH_VDD_LIMIT_OFFSET) | \ 68 (0x1A << AVS_LOW_VDD_LIMIT_OFFSET) | \ 69 (0x1 << AVS_SOFT_RESET_OFFSET) | \ 70 (0x1 << AVS_ENABLE_OFFSET)) 71 /* VDD limit is 1.0V for all A80x0 devices */ 72 #define AVS_A8K_CLK_VALUE ((0x80 << AVS_TARGET_DELTA_OFFSET) | \ 73 (0x24 << AVS_HIGH_VDD_LIMIT_OFFSET) | \ 74 (0x24 << AVS_LOW_VDD_LIMIT_OFFSET) | \ 75 (0x1 << AVS_SOFT_RESET_OFFSET) | \ 76 (0x1 << AVS_ENABLE_OFFSET)) 77 78 /* VDD is 0.88V for 2GHz clock on CN913x devices */ 79 #define AVS_AP807_CLK_VALUE ((0x80UL << 24) | \ 80 (0x2dc << 13) | \ 81 (0x2dc << 3) | \ 82 (0x1 << AVS_SOFT_RESET_OFFSET) | \ 83 (0x1 << AVS_ENABLE_OFFSET)) 84 85 #define MVEBU_AP_EFUSE_SRV_CTRL_REG (MVEBU_AP_GEN_MGMT_BASE + 0x8) 86 #define EFUSE_SRV_CTRL_LD_SELECT_OFFS 6 87 #define EFUSE_SRV_CTRL_LD_SEL_USER_MASK (1 << EFUSE_SRV_CTRL_LD_SELECT_OFFS) 88 89 90 /* 91 * - Identification information in the LD-0 eFuse: 92 * DRO: LD0[74:65] - Not used by the SW 93 * Revision: LD0[78:75] - Not used by the SW 94 * Bin: LD0[80:79] - Not used by the SW 95 * SW Revision: LD0[115:113] 96 * Cluster 1 PWR: LD0[193] - if set to 1, power down CPU Cluster-1 97 * resulting in 2 CPUs active only (7020) 98 */ 99 #define MVEBU_AP_LD_EFUSE_BASE (MVEBU_AP_GEN_MGMT_BASE + 0xF00) 100 /* Bits [94:63] - 32 data bits total */ 101 #define MVEBU_AP_LD0_94_63_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x8) 102 /* Bits [125:95] - 31 data bits total, 32nd bit is parity for bits [125:63] */ 103 #define MVEBU_AP_LD0_125_95_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0xC) 104 /* Bits [220:189] - 32 data bits total */ 105 #define MVEBU_AP_LD0_220_189_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x18) 106 /* Offsets for the above 2 fields combined into single 64-bit value [125:63] */ 107 #define EFUSE_AP_LD0_DRO_OFFS 2 /* LD0[74:65] */ 108 #define EFUSE_AP_LD0_DRO_MASK 0x3FF 109 #define EFUSE_AP_LD0_REVID_OFFS 12 /* LD0[78:75] */ 110 #define EFUSE_AP_LD0_REVID_MASK 0xF 111 #define EFUSE_AP_LD0_BIN_OFFS 16 /* LD0[80:79] */ 112 #define EFUSE_AP_LD0_BIN_MASK 0x3 113 #define EFUSE_AP_LD0_SWREV_OFFS 50 /* LD0[115:113] */ 114 #define EFUSE_AP_LD0_SWREV_MASK 0x7 115 116 #ifndef MVEBU_SOC_AP807 117 /* AP806 AVS work points in the LD0 eFuse 118 * SVC1 work point: LD0[88:81] 119 * SVC2 work point: LD0[96:89] 120 * SVC3 work point: LD0[104:97] 121 * SVC4 work point: LD0[112:105] 122 */ 123 #define EFUSE_AP_LD0_SVC1_OFFS 18 /* LD0[88:81] */ 124 #define EFUSE_AP_LD0_SVC2_OFFS 26 /* LD0[96:89] */ 125 #define EFUSE_AP_LD0_SVC3_OFFS 34 /* LD0[104:97] */ 126 #define EFUSE_AP_LD0_WP_MASK 0xFF 127 #else 128 /* AP807 AVS work points in the LD0 eFuse 129 * SVC1 work point: LD0[91:81] 130 * SVC2 work point: LD0[102:92] 131 * SVC3 work point: LD0[113:103] 132 */ 133 #define EFUSE_AP_LD0_SVC1_OFFS 17 /* LD0[91:81] */ 134 #define EFUSE_AP_LD0_SVC2_OFFS 28 /* LD0[102:92] */ 135 #define EFUSE_AP_LD0_SVC3_OFFS 39 /* LD0[113:103] */ 136 #define EFUSE_AP_LD0_WP_MASK 0x3FF 137 #endif 138 139 #define EFUSE_AP_LD0_SVC4_OFFS 42 /* LD0[112:105] */ 140 141 #define EFUSE_AP_LD0_CLUSTER_DOWN_OFFS 4 142 143 #if MARVELL_SVC_TEST 144 #define MVEBU_CP_MPP_CTRL37_OFFS 20 145 #define MVEBU_CP_MPP_CTRL38_OFFS 24 146 #define MVEBU_CP_MPP_I2C_FUNC 2 147 #define MVEBU_MPP_CTRL_MASK 0xf 148 #endif 149 150 /* Return the AP revision of the chip */ 151 static unsigned int ble_get_ap_type(void) 152 { 153 unsigned int chip_rev_id; 154 155 chip_rev_id = mmio_read_32(MVEBU_CSS_GWD_CTRL_IIDR2_REG); 156 chip_rev_id = ((chip_rev_id & GWD_IIDR2_CHIP_ID_MASK) >> 157 GWD_IIDR2_CHIP_ID_OFFSET); 158 159 return chip_rev_id; 160 } 161 162 /****************************************************************************** 163 * The routine allows to save the CCU and IO windows configuration during DRAM 164 * setup and restore them afterwards before exiting the BLE stage. 165 * Such window configuration is required since not all default settings coming 166 * from the HW and the BootROM allow access to peripherals connected to 167 * all available CPn components. 168 * For instance, when the boot device is located on CP0, the IO window to CP1 169 * is not opened automatically by the HW and if the DRAM SPD is located on CP1 170 * i2c channel, it cannot be read at BLE stage. 171 * Therefore the DRAM init procedure have to provide access to all available 172 * CPn peripherals during the BLE stage by setting the CCU IO window to all 173 * CPnph addresses and by enabling the IO windows accordingly. 174 * Additionally this function configures the CCU GCR to DRAM, which allows 175 * usage or more than 4GB DRAM as it configured by the default CCU DRAM window. 176 * 177 * IN: 178 * MMAP_SAVE_AND_CONFIG - save the existing configuration and update it 179 * MMAP_RESTORE_SAVED - restore saved configuration 180 * OUT: 181 * NONE 182 **************************************************************************** 183 */ 184 static void ble_plat_mmap_config(int restore) 185 { 186 if (restore == MMAP_RESTORE_SAVED) { 187 /* Restore all orig. settings that were modified by BLE stage */ 188 ccu_restore_win_all(MVEBU_AP0); 189 /* Restore CCU */ 190 iow_restore_win_all(MVEBU_AP0); 191 return; 192 } 193 194 /* Store original values */ 195 ccu_save_win_all(MVEBU_AP0); 196 /* Save CCU */ 197 iow_save_win_all(MVEBU_AP0); 198 199 init_ccu(MVEBU_AP0); 200 /* The configuration saved, now all the changes can be done */ 201 init_io_win(MVEBU_AP0); 202 } 203 204 /**************************************************************************** 205 * Setup Adaptive Voltage Switching - this is required for some platforms 206 **************************************************************************** 207 */ 208 #if !MARVELL_SVC_TEST 209 static void ble_plat_avs_config(void) 210 { 211 uint32_t freq_mode, device_id; 212 uint32_t avs_val = 0; 213 214 freq_mode = 215 SAR_CLOCK_FREQ_MODE(mmio_read_32(MVEBU_AP_SAR_REG_BASE( 216 FREQ_MODE_AP_SAR_REG_NUM))); 217 /* Check which SoC is running and act accordingly */ 218 if (ble_get_ap_type() == CHIP_ID_AP807) { 219 avs_val = AVS_AP807_CLK_VALUE; 220 } else { 221 /* Check which SoC is running and act accordingly */ 222 device_id = cp110_device_id_get(MVEBU_CP_REGS_BASE(0)); 223 switch (device_id) { 224 case MVEBU_80X0_DEV_ID: 225 case MVEBU_80X0_CP115_DEV_ID: 226 /* Always fix the default AVS value on A80x0 */ 227 avs_val = AVS_A8K_CLK_VALUE; 228 break; 229 case MVEBU_70X0_DEV_ID: 230 case MVEBU_70X0_CP115_DEV_ID: 231 /* Fix AVS for CPU clocks lower than 1600MHz on A70x0 */ 232 if ((freq_mode > CPU_1600_DDR_900_RCLK_900_2) && 233 (freq_mode < CPU_DDR_RCLK_INVALID)) 234 avs_val = AVS_A7K_LOW_CLK_VALUE; 235 break; 236 default: 237 ERROR("Unsupported Device ID 0x%x\n", device_id); 238 return; 239 } 240 } 241 242 if (avs_val) { 243 VERBOSE("AVS: Setting AVS CTRL to 0x%x\n", avs_val); 244 mmio_write_32(AVS_EN_CTRL_REG, avs_val); 245 } 246 } 247 #endif 248 /****************************************************************************** 249 * Update or override current AVS work point value using data stored in EEPROM 250 * This is only required by QA/validation flows and activated by 251 * MARVELL_SVC_TEST flag. 252 * 253 * The function is expected to be called twice. 254 * 255 * First time with AVS value of 0 for testing if the EEPROM requests completely 256 * override the AVS value and bypass the eFuse test 257 * 258 * Second time - with non-zero AVS value obtained from eFuses as an input. 259 * In this case the EEPROM may contain AVS correction value (either positive 260 * or negative) that is added to the input AVS value and returned back for 261 * further processing. 262 ****************************************************************************** 263 */ 264 static uint32_t avs_update_from_eeprom(uint32_t avs_workpoint) 265 { 266 uint32_t new_wp = avs_workpoint; 267 #if MARVELL_SVC_TEST 268 /* --------------------------------------------------------------------- 269 * EEPROM | Data description (avs_step) 270 * address | 271 * --------------------------------------------------------------------- 272 * 0x120 | AVS workpoint correction value 273 * | if not 0 and not 0xff, correct the AVS taken from eFuse 274 * | by the number of steps indicated by bit[6:0] 275 * | bit[7] defines correction direction. 276 * | If bit[7]=1, add the value from bit[6:0] to AVS workpoint, 277 * | othervise substruct this value from AVS workpoint. 278 * --------------------------------------------------------------------- 279 * 0x121 | AVS workpoint override value 280 * | Override the AVS workpoint with the value stored in this 281 * | byte. When running on AP806, the AVS workpoint is 7 bits 282 * | wide and override value is valid when bit[6:0] holds 283 * | value greater than zero and smaller than 0x33. 284 * | When running on AP807, the AVS workpoint is 10 bits wide. 285 * | Additional 2 MSB bits are supplied by EEPROM byte 0x122. 286 * | AVS override value is valid when byte @ 0x121 and bit[1:0] 287 * | of byte @ 0x122 combined have non-zero value. 288 * --------------------------------------------------------------------- 289 * 0x122 | Extended AVS workpoint override value 290 * | Valid only for AP807 platforms and must be less than 0x4 291 * --------------------------------------------------------------------- 292 */ 293 static uint8_t avs_step[3] = {0}; 294 uintptr_t reg; 295 uint32_t val; 296 unsigned int ap_type = ble_get_ap_type(); 297 298 /* Always happens on second call to this function */ 299 if (avs_workpoint != 0) { 300 /* Get correction steps from the EEPROM */ 301 if ((avs_step[0] != 0) && (avs_step[0] != 0xff)) { 302 NOTICE("AVS request to step %s by 0x%x from old 0x%x\n", 303 avs_step[0] & 0x80 ? "DOWN" : "UP", 304 avs_step[0] & 0x7f, new_wp); 305 if (avs_step[0] & 0x80) 306 new_wp -= avs_step[0] & 0x7f; 307 else 308 new_wp += avs_step[0] & 0x7f; 309 } 310 311 return new_wp; 312 } 313 314 /* AVS values are located in EEPROM 315 * at CP0 i2c bus #0, device 0x57 offset 0x120 316 * The SDA and SCK pins of CP0 i2c-0: MPP[38:37], i2c function 0x2. 317 */ 318 reg = MVEBU_CP_MPP_REGS(0, 4); 319 val = mmio_read_32(reg); 320 val &= ~((MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL37_OFFS) | 321 (MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL38_OFFS)); 322 val |= (MVEBU_CP_MPP_I2C_FUNC << MVEBU_CP_MPP_CTRL37_OFFS) | 323 (MVEBU_CP_MPP_I2C_FUNC << MVEBU_CP_MPP_CTRL38_OFFS); 324 mmio_write_32(reg, val); 325 326 /* Init CP0 i2c-0 */ 327 i2c_init((void *)(MVEBU_CP0_I2C_BASE)); 328 329 /* Read EEPROM only once at the fist call! */ 330 i2c_read(AVS_I2C_EEPROM_ADDR, 0x120, 2, avs_step, 3); 331 NOTICE("== SVC test build ==\n"); 332 NOTICE("EEPROM holds values 0x%x, 0x%x and 0x%x\n", 333 avs_step[0], avs_step[1], avs_step[2]); 334 335 /* Override the AVS value? */ 336 if ((ap_type != CHIP_ID_AP807) && (avs_step[1] < 0x33)) { 337 /* AP806 - AVS is 7 bits */ 338 new_wp = avs_step[1]; 339 340 } else if (ap_type == CHIP_ID_AP807 && (avs_step[2] < 0x4)) { 341 /* AP807 - AVS is 10 bits */ 342 new_wp = avs_step[2]; 343 new_wp <<= 8; 344 new_wp |= avs_step[1]; 345 } 346 347 if (new_wp == 0) 348 NOTICE("Ignore BAD AVS Override value in EEPROM!\n"); 349 else 350 NOTICE("Override AVS by EEPROM value 0x%x\n", new_wp); 351 #endif /* MARVELL_SVC_TEST */ 352 return new_wp; 353 } 354 355 /**************************************************************************** 356 * SVC flow - v0.10 357 * The feature is intended to configure AVS value according to eFuse values 358 * that are burned individually for each SoC during the test process. 359 * Primary AVS value is stored in HD efuse and processed on power on 360 * by the HW engine 361 * Secondary AVS value is located in LD efuse and contains 4 work points for 362 * various CPU frequencies. 363 * The Secondary AVS value is only taken into account if the SW Revision stored 364 * in the efuse is greater than 0 and the CPU is running in a certain speed. 365 **************************************************************************** 366 */ 367 static void ble_plat_svc_config(void) 368 { 369 uint32_t reg_val, avs_workpoint, freq_pidi_mode; 370 uint64_t efuse; 371 uint32_t device_id, single_cluster; 372 uint16_t svc[4], perr[4], i, sw_ver; 373 unsigned int ap_type; 374 375 /* Set access to LD0 */ 376 avs_workpoint = avs_update_from_eeprom(0); 377 if (avs_workpoint) 378 goto set_aws_wp; 379 380 /* Set access to LD0 */ 381 reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG); 382 reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_OFFS; 383 mmio_write_32(MVEBU_AP_EFUSE_SRV_CTRL_REG, reg_val); 384 385 /* Obtain the value of LD0[125:63] */ 386 efuse = mmio_read_32(MVEBU_AP_LD0_125_95_EFUSE_OFFS); 387 efuse <<= 32; 388 efuse |= mmio_read_32(MVEBU_AP_LD0_94_63_EFUSE_OFFS); 389 390 /* SW Revision: 391 * Starting from SW revision 1 the SVC flow is supported. 392 * SW version 0 (efuse not programmed) should follow the 393 * regular AVS update flow. 394 */ 395 sw_ver = (efuse >> EFUSE_AP_LD0_SWREV_OFFS) & EFUSE_AP_LD0_SWREV_MASK; 396 if (sw_ver < 1) { 397 NOTICE("SVC: SW Revision 0x%x. SVC is not supported\n", sw_ver); 398 #if MARVELL_SVC_TEST 399 NOTICE("SVC_TEST: AVS bypassed\n"); 400 401 #else 402 ble_plat_avs_config(); 403 #endif 404 return; 405 } 406 407 /* Frequency mode from SAR */ 408 freq_pidi_mode = SAR_CLOCK_FREQ_MODE( 409 mmio_read_32( 410 MVEBU_AP_SAR_REG_BASE( 411 FREQ_MODE_AP_SAR_REG_NUM))); 412 413 /* Decode all SVC work points */ 414 svc[0] = (efuse >> EFUSE_AP_LD0_SVC1_OFFS) & EFUSE_AP_LD0_WP_MASK; 415 svc[1] = (efuse >> EFUSE_AP_LD0_SVC2_OFFS) & EFUSE_AP_LD0_WP_MASK; 416 svc[2] = (efuse >> EFUSE_AP_LD0_SVC3_OFFS) & EFUSE_AP_LD0_WP_MASK; 417 418 /* Fetch AP type to distinguish between AP806 and AP807 */ 419 ap_type = ble_get_ap_type(); 420 421 if (ap_type != CHIP_ID_AP807) { 422 svc[3] = (efuse >> EFUSE_AP_LD0_SVC4_OFFS) 423 & EFUSE_AP_LD0_WP_MASK; 424 INFO("SVC: Efuse WP: [0]=0x%x, [1]=0x%x, [2]=0x%x, [3]=0x%x\n", 425 svc[0], svc[1], svc[2], svc[3]); 426 } else { 427 INFO("SVC: Efuse WP: [0]=0x%x, [1]=0x%x, [2]=0x%x\n", 428 svc[0], svc[1], svc[2]); 429 } 430 431 /* Validate parity of SVC workpoint values */ 432 for (i = 0; i < 4; i++) { 433 uint8_t parity, bit; 434 435 perr[i] = 0; 436 437 for (bit = 1, parity = svc[i] & 1; bit < 7; bit++) 438 parity ^= (svc[i] >> bit) & 1; 439 440 /* Starting from SW version 2, the parity check is mandatory */ 441 if ((sw_ver > 1) && (parity != ((svc[i] >> 7) & 1))) 442 perr[i] = 1; /* register the error */ 443 } 444 445 single_cluster = mmio_read_32(MVEBU_AP_LD0_220_189_EFUSE_OFFS); 446 single_cluster = (single_cluster >> EFUSE_AP_LD0_CLUSTER_DOWN_OFFS) & 1; 447 448 device_id = cp110_device_id_get(MVEBU_CP_REGS_BASE(0)); 449 if (device_id == MVEBU_80X0_DEV_ID || 450 device_id == MVEBU_80X0_CP115_DEV_ID) { 451 /* A8040/A8020 */ 452 NOTICE("SVC: DEV ID: %s, FREQ Mode: 0x%x\n", 453 single_cluster == 0 ? "8040" : "8020", freq_pidi_mode); 454 switch (freq_pidi_mode) { 455 case CPU_1800_DDR_1050_RCLK_1050: 456 if (perr[1]) 457 goto perror; 458 avs_workpoint = svc[1]; 459 break; 460 case CPU_1600_DDR_1050_RCLK_1050: 461 case CPU_1600_DDR_900_RCLK_900_2: 462 if (perr[2]) 463 goto perror; 464 avs_workpoint = svc[2]; 465 break; 466 case CPU_1300_DDR_800_RCLK_800: 467 case CPU_1300_DDR_650_RCLK_650: 468 if (perr[3]) 469 goto perror; 470 avs_workpoint = svc[3]; 471 break; 472 case CPU_2000_DDR_1200_RCLK_1200: 473 case CPU_2000_DDR_1050_RCLK_1050: 474 default: 475 if (perr[0]) 476 goto perror; 477 avs_workpoint = svc[0]; 478 break; 479 } 480 } else if (device_id == MVEBU_70X0_DEV_ID || 481 device_id == MVEBU_70X0_CP115_DEV_ID) { 482 /* A7040/A7020/A6040 */ 483 NOTICE("SVC: DEV ID: %s, FREQ Mode: 0x%x\n", 484 single_cluster == 0 ? "7040" : "7020", freq_pidi_mode); 485 switch (freq_pidi_mode) { 486 case CPU_1400_DDR_800_RCLK_800: 487 if (single_cluster) {/* 7020 */ 488 if (perr[1]) 489 goto perror; 490 avs_workpoint = svc[1]; 491 } else { 492 if (perr[0]) 493 goto perror; 494 avs_workpoint = svc[0]; 495 } 496 break; 497 case CPU_1200_DDR_800_RCLK_800: 498 if (single_cluster) {/* 7020 */ 499 if (perr[2]) 500 goto perror; 501 avs_workpoint = svc[2]; 502 } else { 503 if (perr[1]) 504 goto perror; 505 avs_workpoint = svc[1]; 506 } 507 break; 508 case CPU_800_DDR_800_RCLK_800: 509 case CPU_1000_DDR_800_RCLK_800: 510 if (single_cluster) {/* 7020 */ 511 if (perr[3]) 512 goto perror; 513 avs_workpoint = svc[3]; 514 } else { 515 if (perr[2]) 516 goto perror; 517 avs_workpoint = svc[2]; 518 } 519 break; 520 case CPU_600_DDR_800_RCLK_800: 521 if (perr[3]) 522 goto perror; 523 avs_workpoint = svc[3]; /* Same for 6040 and 7020 */ 524 break; 525 case CPU_1600_DDR_800_RCLK_800: /* 7020 only */ 526 default: 527 if (single_cluster) {/* 7020 */ 528 if (perr[0]) 529 goto perror; 530 avs_workpoint = svc[0]; 531 } else { 532 #if MARVELL_SVC_TEST 533 reg_val = mmio_read_32(AVS_EN_CTRL_REG); 534 avs_workpoint = (reg_val & 535 AVS_VDD_LOW_LIMIT_MASK) >> 536 AVS_LOW_VDD_LIMIT_OFFSET; 537 NOTICE("7040 1600Mhz, avs = 0x%x\n", 538 avs_workpoint); 539 #else 540 avs_workpoint = 0; 541 #endif 542 } 543 break; 544 } 545 } else if (device_id == MVEBU_3900_DEV_ID) { 546 NOTICE("SVC: DEV ID: %s, FREQ Mode: 0x%x\n", 547 "3900", freq_pidi_mode); 548 switch (freq_pidi_mode) { 549 case CPU_1600_DDR_1200_RCLK_1200: 550 if (perr[0]) 551 goto perror; 552 avs_workpoint = svc[0]; 553 break; 554 case CPU_1300_DDR_800_RCLK_800: 555 if (perr[1]) 556 goto perror; 557 avs_workpoint = svc[1]; 558 break; 559 default: 560 if (perr[0]) 561 goto perror; 562 avs_workpoint = svc[0]; 563 break; 564 } 565 } else { 566 ERROR("SVC: Unsupported Device ID 0x%x\n", device_id); 567 return; 568 } 569 570 /* Set AVS control if needed */ 571 if (avs_workpoint == 0) { 572 ERROR("SVC: AVS work point not changed\n"); 573 return; 574 } 575 576 /* Remove parity bit */ 577 if (ap_type != CHIP_ID_AP807) 578 avs_workpoint &= 0x7F; 579 580 /* Update WP from EEPROM if needed */ 581 avs_workpoint = avs_update_from_eeprom(avs_workpoint); 582 583 set_aws_wp: 584 reg_val = mmio_read_32(AVS_EN_CTRL_REG); 585 NOTICE("SVC: AVS work point changed from 0x%x to 0x%x\n", 586 (reg_val & AVS_VDD_LOW_LIMIT_MASK) >> AVS_LOW_VDD_LIMIT_OFFSET, 587 avs_workpoint); 588 reg_val &= ~(AVS_VDD_LOW_LIMIT_MASK | AVS_VDD_HIGH_LIMIT_MASK); 589 reg_val |= 0x1 << AVS_ENABLE_OFFSET; 590 reg_val |= avs_workpoint << AVS_HIGH_VDD_LIMIT_OFFSET; 591 reg_val |= avs_workpoint << AVS_LOW_VDD_LIMIT_OFFSET; 592 mmio_write_32(AVS_EN_CTRL_REG, reg_val); 593 return; 594 595 perror: 596 ERROR("Failed SVC WP[%d] parity check!\n", i); 597 ERROR("Ignoring the WP values\n"); 598 } 599 600 #if PLAT_RECOVERY_IMAGE_ENABLE 601 static int ble_skip_image_i2c(struct skip_image *skip_im) 602 { 603 ERROR("skipping image using i2c is not supported\n"); 604 /* not supported */ 605 return 0; 606 } 607 608 static int ble_skip_image_other(struct skip_image *skip_im) 609 { 610 ERROR("implementation missing for skip image request\n"); 611 /* not supported, make your own implementation */ 612 return 0; 613 } 614 615 static int ble_skip_image_gpio(struct skip_image *skip_im) 616 { 617 unsigned int val; 618 unsigned int mpp_address = 0; 619 unsigned int offset = 0; 620 621 switch (skip_im->info.test.cp_ap) { 622 case(CP): 623 mpp_address = MVEBU_CP_GPIO_DATA_IN(skip_im->info.test.cp_index, 624 skip_im->info.gpio.num); 625 if (skip_im->info.gpio.num > NUM_OF_GPIO_PER_REG) 626 offset = skip_im->info.gpio.num - NUM_OF_GPIO_PER_REG; 627 else 628 offset = skip_im->info.gpio.num; 629 break; 630 case(AP): 631 mpp_address = MVEBU_AP_GPIO_DATA_IN; 632 offset = skip_im->info.gpio.num; 633 break; 634 } 635 636 val = mmio_read_32(mpp_address); 637 val &= (1 << offset); 638 if ((!val && skip_im->info.gpio.button_state == HIGH) || 639 (val && skip_im->info.gpio.button_state == LOW)) { 640 mmio_write_32(SCRATCH_PAD_REG2, SCRATCH_PAD_SKIP_VAL); 641 return 1; 642 } 643 644 return 0; 645 } 646 647 /* 648 * This function checks if there's a skip image request: 649 * return values: 650 * 1: (true) images request been made. 651 * 0: (false) no image request been made. 652 */ 653 static int ble_skip_current_image(void) 654 { 655 struct skip_image *skip_im; 656 657 /*fetching skip image info*/ 658 skip_im = (struct skip_image *)plat_marvell_get_skip_image_data(); 659 660 if (skip_im == NULL) 661 return 0; 662 663 /* check if skipping image request has already been made */ 664 if (mmio_read_32(SCRATCH_PAD_REG2) == SCRATCH_PAD_SKIP_VAL) 665 return 0; 666 667 switch (skip_im->detection_method) { 668 case GPIO: 669 return ble_skip_image_gpio(skip_im); 670 case I2C: 671 return ble_skip_image_i2c(skip_im); 672 case USER_DEFINED: 673 return ble_skip_image_other(skip_im); 674 } 675 676 return 0; 677 } 678 #endif 679 680 681 int ble_plat_setup(int *skip) 682 { 683 int ret; 684 unsigned int freq_mode; 685 686 /* Power down unused CPUs */ 687 plat_marvell_early_cpu_powerdown(); 688 689 /* 690 * Save the current CCU configuration and make required changes: 691 * - Allow access to DRAM larger than 4GB 692 * - Open memory access to all CPn peripherals 693 */ 694 ble_plat_mmap_config(MMAP_SAVE_AND_CONFIG); 695 696 #if PLAT_RECOVERY_IMAGE_ENABLE 697 /* Check if there's a skip request to bootRom recovery Image */ 698 if (ble_skip_current_image()) { 699 /* close memory access to all CPn peripherals. */ 700 ble_plat_mmap_config(MMAP_RESTORE_SAVED); 701 *skip = 1; 702 return 0; 703 } 704 #endif 705 /* Do required CP-110 setups for BLE stage */ 706 cp110_ble_init(MVEBU_CP_REGS_BASE(0)); 707 708 /* Setup AVS */ 709 ble_plat_svc_config(); 710 711 /* read clk option from sampled-at-reset register */ 712 freq_mode = 713 SAR_CLOCK_FREQ_MODE(mmio_read_32(MVEBU_AP_SAR_REG_BASE( 714 FREQ_MODE_AP_SAR_REG_NUM))); 715 716 /* work with PLL clock driver in AP807 */ 717 if (ble_get_ap_type() == CHIP_ID_AP807) 718 ap807_clocks_init(freq_mode); 719 720 /* Do required AP setups for BLE stage */ 721 ap_ble_init(); 722 723 /* Update DRAM topology (scan DIMM SPDs) */ 724 plat_marvell_dram_update_topology(); 725 726 /* Kick it in */ 727 ret = dram_init(); 728 729 /* Restore the original CCU configuration before exit from BLE */ 730 ble_plat_mmap_config(MMAP_RESTORE_SAVED); 731 732 return ret; 733 } 734