Merge "fix(intel): bl31 overwrite OCRAM configuration" into integration

Merge "fix(intel): update DDR range checking for Agilex5" into integration

Merge "fix(intel): update fcs functions to check ddr range" into integration

Merge "feat(intel): support SDM mailbox safe inject seu error for Linux" into integration

feat(intel): enable SDMMC frontdoor load for ATF->Linux

SDMMC is 1 of the boot source for Agilex5 and legacy products.
By enabling this, ATF is able to read out the DTB binary and
loaded it to DDR f

feat(intel): enable SDMMC frontdoor load for ATF->Linux

SDMMC is 1 of the boot source for Agilex5 and legacy products.
By enabling this, ATF is able to read out the DTB binary and
loaded it to DDR for Linux boot.

Change-Id: Ida303fb43ea63013a08083ce65952c5ad4e28f93
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

show more ...

fix(intel): fix hardcoded mpu frequency ticks

This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.

Change-Id: I7b9eb49f2512b85fb477110f06a

fix(intel): fix hardcoded mpu frequency ticks

This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.

Change-Id: I7b9eb49f2512b85fb477110f06ae86ef289aee58
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

show more ...

feat(intel): support SDM mailbox safe inject seu error for Linux

Linux RAS shall handle the SEU error received from SDM and report
an error message to user

Change-Id: I89181a388063ce9bd6f56b45b1851

feat(intel): support SDM mailbox safe inject seu error for Linux

Linux RAS shall handle the SEU error received from SDM and report
an error message to user

Change-Id: I89181a388063ce9bd6f56b45b1851ccb08582437
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

show more ...

fix(intel): update DDR range checking for Agilex5

Update DDR range checking for Agilex when total max size of
DRAM_BASE and DRAM_SIZE overflow unsigned 64bit.

Change-Id: Iaecfa5daae48da0af46cc1831d

fix(intel): update DDR range checking for Agilex5

Update DDR range checking for Agilex when total max size of
DRAM_BASE and DRAM_SIZE overflow unsigned 64bit.

Change-Id: Iaecfa5daae48da0af46cc1831d10c0e6a79613c2
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

show more ...

fix(intel): update fcs functions to check ddr range

The src addr and dest addr of fcs functions are not checked against
their valid ddr range. Thus adding the ddr range checking to avoid
overlap/ove

fix(intel): update fcs functions to check ddr range

The src addr and dest addr of fcs functions are not checked against
their valid ddr range. Thus adding the ddr range checking to avoid
overlap/overwritten ddr address.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I9b4d4155dd16d9d5d36e0c91e4a2600c17867daf

show more ...

fix(intel): update fcs crypto init code to check for mode

The shall code only limit ECB, CBC and CTR mode to flow through the init
function. Anything other than that, the code shall reject to preven

fix(intel): update fcs crypto init code to check for mode

The shall code only limit ECB, CBC and CTR mode to flow through the init
function. Anything other than that, the code shall reject to prevent
security vulnerability.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I702ce90e229188830f8936bee2999610e9559b8b

show more ...

Merge "fix(intel): update HPS bridges for Agilex5 SoC FPGA" into integration

Merge "fix(intel): read QSPI bank buffer data in bytes" into integration

Merge "fix(intel): temporarily workaround for Zephyr SMP" into integration

Merge "feat(intel): restructure watchdog" into integration

Merge "fix(intel): update individual return result for hps and fpga bridges" into integration

Merge "feat(intel): increase bl2 size limit" into integration

Merge "fix(intel): update stream id to non-secure for SDM" into integration

Merge "fix(intel): revert sys counter to 400MHz" into integration

fix(intel): read QSPI bank buffer data in bytes

Read QSPI bank buffer data in bytes to avoid
inter-bank read failures.

Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Change-Id: If768d7cdd36

fix(intel): read QSPI bank buffer data in bytes

Read QSPI bank buffer data in bytes to avoid
inter-bank read failures.

Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Change-Id: If768d7cdd362694df3f3c86c959afad01a523f21

show more ...

fix(intel): bl31 overwrite OCRAM configuration

U-boot is allowed to configure OCRAM access. However
ATF BL31 will overwrite it. Thus removing this function
to allow for proper configuration.

Change

fix(intel): bl31 overwrite OCRAM configuration

U-boot is allowed to configure OCRAM access. However
ATF BL31 will overwrite it. Thus removing this function
to allow for proper configuration.

Change-Id: I45173ef8f472c3620486de0cbf6452ba5f78be01
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

show more ...

fix(intel): update individual return result for hps and fpga bridges

The code is designed to execute SOC2FPGA and LWSOC2FPGA first
then to F2SOC and both sharing the same result "return".
Thus when

fix(intel): update individual return result for hps and fpga bridges

The code is designed to execute SOC2FPGA and LWSOC2FPGA first
then to F2SOC and both sharing the same result "return".
Thus when F2SOC is executed, the "return" result will overwrite
SOC2FPGA "return" result even though it is not enabled.
Using 2 different "return" result to for each bridges and
return both of them at the end of the function to
avoid being overwritten.

Change-Id: Id9de3f416fe3020db35bc946135b175be2a7dc1e
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

show more ...

feat(intel): increase bl2 size limit

There are several features included in BL2 causing the size getting
bigger for RELEASE mode. When build with DEBUG mode, the size will
be bigger thus causing BL2

feat(intel): increase bl2 size limit

There are several features included in BL2 causing the size getting
bigger for RELEASE mode. When build with DEBUG mode, the size will
be bigger thus causing BL2 image has exceeded its limits.

Change-Id: I7542f5ea001542450695d48e8126bcca8728d76a
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

show more ...

fix(intel): update stream id to non-secure for SDM

Update stream id to non-secure for SDM which is to
bring up FPGA config via SMMU.

Change-Id: Ib8836fa0cf31fe0cfc0261123e051772923bb66b
Signed-off-

fix(intel): update stream id to non-secure for SDM

Update stream id to non-secure for SDM which is to
bring up FPGA config via SMMU.

Change-Id: Ib8836fa0cf31fe0cfc0261123e051772923bb66b
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

show more ...

fix(intel): revert sys counter to 400MHz

For Simics and official release, revert back to 400MHz instead of
80MHz. Sys counter shall get from a static clock.

Change-Id: I9ee3586bc411af8d7381c8bd6404

fix(intel): revert sys counter to 400MHz

For Simics and official release, revert back to 400MHz instead of
80MHz. Sys counter shall get from a static clock.

Change-Id: I9ee3586bc411af8d7381c8bd6404b8449b0c3f69
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

show more ...

fix(intel): update HPS bridges for Agilex5 SoC FPGA

This patch is used to update reset manager support
for Agilex5 Soc FPGA.
1. Update HPS bridges support for socfpga_bridges_disable
a. SOC2FPGA

fix(intel): update HPS bridges for Agilex5 SoC FPGA

This patch is used to update reset manager support
for Agilex5 Soc FPGA.
1. Update HPS bridges support for socfpga_bridges_disable
a. SOC2FPGA
b. LWSOC2FPGA
c. F2SDRAM
d. F2SOC

Change-Id: Ia539ff289e83303ae3b4d78b9ac1d50c9f9558da
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

show more ...