1/* 2 * Copyright (c) 2020-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10#include <neoverse_n2.h> 11#include "wa_cve_2022_23960_bhb_vector.S" 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18/* 64-bit only core */ 19#if CTX_INCLUDE_AARCH32_REGS == 1 20#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 21#endif 22 23#if WORKAROUND_CVE_2022_23960 24 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2 25#endif /* WORKAROUND_CVE_2022_23960 */ 26 27/* 28 * ERRATA_DSU_2313941: 29 * The errata is defined in dsu_helpers.S and applies to Neoverse N2. 30 * Henceforth creating symbolic names to the already existing errata 31 * workaround functions to get them registered under the Errata Framework. 32 */ 33.equ check_erratum_neoverse_n2_2313941, check_errata_dsu_2313941 34.equ erratum_neoverse_n2_2313941_wa, errata_dsu_2313941_wa 35add_erratum_entry neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET 36 37workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655 38 /* Apply instruction patching sequence */ 39 ldr x0,=0x6 40 msr S3_6_c15_c8_0,x0 41 ldr x0,=0xF3A08002 42 msr S3_6_c15_c8_2,x0 43 ldr x0,=0xFFF0F7FE 44 msr S3_6_c15_c8_3,x0 45 ldr x0,=0x40000001003ff 46 msr S3_6_c15_c8_1,x0 47 ldr x0,=0x7 48 msr S3_6_c15_c8_0,x0 49 ldr x0,=0xBF200000 50 msr S3_6_c15_c8_2,x0 51 ldr x0,=0xFFEF0000 52 msr S3_6_c15_c8_3,x0 53 ldr x0,=0x40000001003f3 54 msr S3_6_c15_c8_1,x0 55workaround_reset_end neoverse_n2, ERRATUM(2002655) 56 57check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0) 58 59workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414 60 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT 61workaround_reset_end neoverse_n2, ERRATUM(2025414) 62 63check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0) 64 65workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956 66 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 67workaround_reset_end neoverse_n2, ERRATUM(2067956) 68 69check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0) 70 71workaround_runtime_start neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478 72 /* Stash ERRSELR_EL1 in x2 */ 73 mrs x2, ERRSELR_EL1 74 75 /* Select error record 0 and clear ED bit */ 76 msr ERRSELR_EL1, xzr 77 mrs x1, ERXCTLR_EL1 78 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 79 msr ERXCTLR_EL1, x1 80 81 /* Restore ERRSELR_EL1 from x2 */ 82 msr ERRSELR_EL1, x2 83workaround_runtime_end neoverse_n2, ERRATUM(2009478), NO_ISB 84 85check_erratum_ls neoverse_n2, ERRATUM(2009478), CPU_REV(0, 0) 86 87workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953 88 /* Apply instruction patching sequence */ 89 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 90 mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV 91 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH 92 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 93workaround_reset_end neoverse_n2, ERRATUM(2138953) 94 95check_erratum_ls neoverse_n2, ERRATUM(2138953), CPU_REV(0, 3) 96 97workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956 98 /* Apply instruction patching sequence */ 99 ldr x0,=0x3 100 msr S3_6_c15_c8_0,x0 101 ldr x0,=0xF3A08002 102 msr S3_6_c15_c8_2,x0 103 ldr x0,=0xFFF0F7FE 104 msr S3_6_c15_c8_3,x0 105 ldr x0,=0x10002001003FF 106 msr S3_6_c15_c8_1,x0 107 ldr x0,=0x4 108 msr S3_6_c15_c8_0,x0 109 ldr x0,=0xBF200000 110 msr S3_6_c15_c8_2,x0 111 ldr x0,=0xFFEF0000 112 msr S3_6_c15_c8_3,x0 113 ldr x0,=0x10002001003F3 114 msr S3_6_c15_c8_1,x0 115workaround_reset_end neoverse_n2, ERRATUM(2138956) 116 117check_erratum_ls neoverse_n2, ERRATUM(2138956), CPU_REV(0, 0) 118 119 120workaround_reset_start neoverse_n2, ERRATUM(2138958), ERRATA_N2_2138958 121 /* Apply instruction patching sequence */ 122 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 123workaround_reset_end neoverse_n2, ERRATUM(2138958) 124 125check_erratum_ls neoverse_n2, ERRATUM(2138958), CPU_REV(0, 0) 126 127workaround_reset_start neoverse_n2, ERRATUM(2189731), ERRATA_N2_2189731 128 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 129workaround_reset_end neoverse_n2, ERRATUM(2189731) 130 131check_erratum_ls neoverse_n2, ERRATUM(2189731), CPU_REV(0, 0) 132 133workaround_reset_start neoverse_n2, ERRATUM(2242400), ERRATA_N2_2242400 134 /* Apply instruction patching sequence */ 135 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 136 ldr x0, =0x2 137 msr S3_6_c15_c8_0, x0 138 ldr x0, =0x10F600E000 139 msr S3_6_c15_c8_2, x0 140 ldr x0, =0x10FF80E000 141 msr S3_6_c15_c8_3, x0 142 ldr x0, =0x80000000003FF 143 msr S3_6_c15_c8_1, x0 144workaround_reset_end neoverse_n2, ERRATUM(2242400) 145 146check_erratum_ls neoverse_n2, ERRATUM(2242400), CPU_REV(0, 0) 147 148workaround_reset_start neoverse_n2, ERRATUM(2242415), ERRATA_N2_2242415 149 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 150workaround_reset_end neoverse_n2, ERRATUM(2242415) 151 152check_erratum_ls neoverse_n2, ERRATUM(2242415), CPU_REV(0, 0) 153 154workaround_reset_start neoverse_n2, ERRATUM(2280757), ERRATA_N2_2280757 155 /* Apply instruction patching sequence */ 156 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 157workaround_reset_end neoverse_n2, ERRATUM(2280757) 158 159check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0) 160 161workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639 162 /* Set bit 36 in ACTLR2_EL1 */ 163 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 164workaround_runtime_end neoverse_n2, ERRATUM(2326639) 165 166check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0) 167 168workaround_reset_start neoverse_n2, ERRATUM(2376738), ERRATA_N2_2376738 169 /* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM 170 * ST to behave like PLD/PFRM LD and not cause 171 * invalidations to other PE caches. 172 */ 173 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 174workaround_reset_end neoverse_n2, ERRATUM(2376738) 175 176check_erratum_ls neoverse_n2, ERRATUM(2376738), CPU_REV(0, 3) 177 178workaround_reset_start neoverse_n2, ERRATUM(2388450), ERRATA_N2_2388450 179 /*Set bit 40 in ACTLR2_EL1 */ 180 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 181workaround_reset_end neoverse_n2, ERRATUM(2388450) 182 183check_erratum_ls neoverse_n2, ERRATUM(2388450), CPU_REV(0, 0) 184 185workaround_reset_start neoverse_n2, ERRATUM(2743014), ERRATA_N2_2743014 186 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 187 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 188 sysreg_bit_clear NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 189workaround_reset_end neoverse_n2, ERRATUM(2743014) 190 191check_erratum_ls neoverse_n2, ERRATUM(2743014), CPU_REV(0, 2) 192 193workaround_runtime_start neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089 194 /* dsb before isb of power down sequence */ 195 dsb sy 196workaround_runtime_end neoverse_n2, ERRATUM(2743089) 197 198check_erratum_ls neoverse_n2, ERRATUM(2743089), CPU_REV(0, 2) 199 200workaround_reset_start neoverse_n2, ERRATUM(2779511), ERRATA_N2_2779511 201 /* Set bit 47 in ACTLR3_EL1 */ 202 sysreg_bit_set NEOVERSE_N2_CPUACTLR3_EL1, NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 203workaround_reset_end neoverse_n2, ERRATUM(2779511) 204 205check_erratum_ls neoverse_n2, ERRATUM(2779511), CPU_REV(0, 2) 206 207workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 208#if IMAGE_BL31 209 /* 210 * The Neoverse-N2 generic vectors are overridden to apply errata 211 * mitigation on exception entry from lower ELs. 212 */ 213 override_vector_table wa_cve_vbar_neoverse_n2 214#endif /* IMAGE_BL31 */ 215workaround_reset_end neoverse_n2, CVE(2022,23960) 216 217check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 218 219 /* ------------------------------------------- 220 * The CPU Ops reset function for Neoverse N2. 221 * ------------------------------------------- 222 */ 223cpu_reset_func_start neoverse_n2 224 225 /* Check if the PE implements SSBS */ 226 mrs x0, id_aa64pfr1_el1 227 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 228 b.eq 1f 229 230 /* Disable speculative loads */ 231 msr SSBS, xzr 2321: 233 /* Force all cacheable atomic instructions to be near */ 234 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 235 236#if ENABLE_FEAT_AMU 237 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 238 sysreg_bit_set cptr_el3, TAM_BIT 239 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 240 sysreg_bit_set cptr_el2, TAM_BIT 241 /* No need to enable the counters as this would be done at el3 exit */ 242#endif 243 244#if NEOVERSE_Nx_EXTERNAL_LLC 245 /* Some systems may have External LLC, core needs to be made aware */ 246 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT 247#endif 248cpu_reset_func_end neoverse_n2 249 250func neoverse_n2_core_pwr_dwn 251 252 apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478 253 apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV 254 255 /* --------------------------------------------------- 256 * Enable CPU power down bit in power control register 257 * No need to do cache maintenance here. 258 * --------------------------------------------------- 259 */ 260 sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT 261 262 apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089 263 264 isb 265 ret 266endfunc neoverse_n2_core_pwr_dwn 267 268errata_report_shim neoverse_n2 269 270 /* --------------------------------------------- 271 * This function provides Neoverse N2 specific 272 * register information for crash reporting. 273 * It needs to return with x6 pointing to 274 * a list of register names in ASCII and 275 * x8 - x15 having values of registers to be 276 * reported. 277 * --------------------------------------------- 278 */ 279.section .rodata.neoverse_n2_regs, "aS" 280neoverse_n2_regs: /* The ASCII list of register names to be reported */ 281 .asciz "cpupwrctlr_el1", "" 282 283func neoverse_n2_cpu_reg_dump 284 adr x6, neoverse_n2_regs 285 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 286 ret 287endfunc neoverse_n2_cpu_reg_dump 288 289declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ 290 neoverse_n2_reset_func, \ 291 neoverse_n2_core_pwr_dwn 292