Merge changes from topic "nrd3_support" into integration

* changes:
feat(rdfremont): add support for measured boot at BL1 and BL2
feat(arm): mock support for CCA NV ctr
feat(rdfremont): fetch

Merge changes from topic "nrd3_support" into integration

* changes:
feat(rdfremont): add support for measured boot at BL1 and BL2
feat(arm): mock support for CCA NV ctr
feat(rdfremont): fetch attestation key and token from RSE
feat(psa): introduce generic library for CCA attestation
feat(rdfremont): initialize the rse comms driver
feat(rdfremont): helper to initialize rse-comms with AP-RSE MHUv3
fix(rse): include lib-psa to resolve build
feat(neoverse-rd): add MHUv3 channels on third gen multichip platforms
feat(neoverse-rd): add MHUv3 doorbell channels on third gen platforms
feat(rdfremont): initialize GPT on GPC SMMU block
feat(rdfremont): update Root registers page offset for SMMUv3
feat(rdfremont): enable MTE2 if present on the platform
feat(rdfremont): enable SVE for SWD and NS
feat(rdfremont): enable AMU if present on the platform
feat(rdfremont): enable MPAM if present on the platform
feat(rdfremont): add DRAM pas entries in pas table for multichip
feat(rdfremont): add implementation for GPT setup
feat(rdfremont): integrate DTS files for RD-Fremont variants
feat(rdfremont): add support for RD-Fremont-Cfg2
feat(rdfremont): add support for RD-Fremont-Cfg1
feat(rdfremont): add support for RD-Fremont
feat(neoverse-rd): add scope for RD-Fremont variants
feat(neoverse-rd): add multichip pas entries
feat(neoverse-rd): add pas definitions for third gen platforms
feat(neoverse-rd): add DRAM layout for third gen platforms
feat(neoverse-rd): add SRAM layout for third gen platforms
feat(neoverse-rd): add firmware definitions for third gen platforms
feat(neoverse-rd): add RoS definitions for third gen platforms
feat(neoverse-rd): add CSS definitions for third gen platforms

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fix(tc): add SCP_BL2 to RSE measured boot

SCP_BL2 is part of CCA's TCB. The SCP_BL1 is loaded
by RSE. It has already added to the platform
attestation token. SCP_BL2 was missed, so it is
fixed now.

fix(tc): add SCP_BL2 to RSE measured boot

SCP_BL2 is part of CCA's TCB. The SCP_BL1 is loaded
by RSE. It has already added to the platform
attestation token. SCP_BL2 was missed, so it is
fixed now.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ic87743564136f03a901c90ff1ec614f5965b9a47

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Merge changes from topic "dualroot_dtb" into integration

* changes:
refactor(fvp): add CoT desc dtsi
feat(arm): add COT_DESC_IN_DTB option for Dualroot
feat(fvp): add Dualroot CoT in DTB suppo

Merge changes from topic "dualroot_dtb" into integration

* changes:
refactor(fvp): add CoT desc dtsi
feat(arm): add COT_DESC_IN_DTB option for Dualroot
feat(fvp): add Dualroot CoT in DTB support
feat(dt-bindings): introduce Dualroot CoT DTB

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feat(rdfremont): add support for measured boot at BL1 and BL2

RD-Fremont platforms include Runtime Security Engine (RSE) as the
hardware crypto module. Add rse_measured_boot driver based platform
ho

feat(rdfremont): add support for measured boot at BL1 and BL2

RD-Fremont platforms include Runtime Security Engine (RSE) as the
hardware crypto module. Add rse_measured_boot driver based platform
hooks to measure and record firmware image measurements.

Additionally, add support for measured boot at BL1 and BL2 boot stages
on RD-Fremont platforms. The patch adds the RSE measured boot metadata
that includes firmware image IDs, measurement slot number and other
information. It also initializes the AP communication with RSE over
AP-RSE root MHUv3 channel to pass firmware image measurements to RSE to
support extended measurements.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ia1b0bf673e865b31862cb8af79c4c71a5ba4dbea

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feat(arm): mock support for CCA NV ctr

Arm reference design FVP platforms such as RD-Fremont do not implement
the CCA_FW_NVCOUNTER. Update firmware such that the implementation will
return TRUSTED_F

feat(arm): mock support for CCA NV ctr

Arm reference design FVP platforms such as RD-Fremont do not implement
the CCA_FW_NVCOUNTER. Update firmware such that the implementation will
return TRUSTED_FW_NVCOUNTER when the caller requests the CCA NV counter.
This allows the platforms to use the CCA CoT on FVP platforms.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ifab724fae63857056b3eeb44eeefc15c4c610eed

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feat(rdfremont): fetch attestation key and token from RSE

Use the delegated attestation driver to fetch platform attestation token
and Realm attestation key from RSE over the AP-RSE comms interface.

feat(rdfremont): fetch attestation key and token from RSE

Use the delegated attestation driver to fetch platform attestation token
and Realm attestation key from RSE over the AP-RSE comms interface.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Id0cfd82ef79598cd8368ba017c145bf34d502e65

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feat(rdfremont): initialize the rse comms driver

Define platform specific API to fetch base address for secure or root
MHUv3 between AP-RSE invoke rse-comms driver initialization bl31
platform setup

feat(rdfremont): initialize the rse comms driver

Define platform specific API to fetch base address for secure or root
MHUv3 between AP-RSE invoke rse-comms driver initialization bl31
platform setup stage.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Id79bcdb2fda6cdf394f4e02f67d1c1a44d5ddf23

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feat(rdfremont): helper to initialize rse-comms with AP-RSE MHUv3

Add a helper function to initialize rse_comms on RD-Fremont platforms
with AP-RSE MHUv3 postbox and mailbox register frames.

Signed

feat(rdfremont): helper to initialize rse-comms with AP-RSE MHUv3

Add a helper function to initialize rse_comms on RD-Fremont platforms
with AP-RSE MHUv3 postbox and mailbox register frames.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ic390517a8810df195a2582793b81afdbff5ffa15

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feat(neoverse-rd): add MHUv3 channels on third gen multichip platforms

Add MHUv3 doorbell channel information to scmi_channel_plat_info_t for
third generation of multichip Neoverse reference design

feat(neoverse-rd): add MHUv3 channels on third gen multichip platforms

Add MHUv3 doorbell channel information to scmi_channel_plat_info_t for
third generation of multichip Neoverse reference design platforms.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ie4ebf47a10f2f6e33c7ecfc8008e30bacc62bf3d

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feat(neoverse-rd): add MHUv3 doorbell channels on third gen platforms

Define and use a new scmi_channel_plat_info_t structure specific to
third generation Neoverse platforms in order to use MHUv3 do

feat(neoverse-rd): add MHUv3 doorbell channels on third gen platforms

Define and use a new scmi_channel_plat_info_t structure specific to
third generation Neoverse platforms in order to use MHUv3 doorbell
channels. The structure uses the existing mhu_ring_doorbell method for
ring_doorbell implementation.

Signed-off-by: Shriram K <shriram.k@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Icf3be5305df94ba944038a4d4fdf0ccf32168650

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feat(rdfremont): initialize GPT on GPC SMMU block

GPC SMMU does granule protection checks (GPC) for accesses originating
from the system control block and GIC on RD-Fremont platforms. The GPC
check

feat(rdfremont): initialize GPT on GPC SMMU block

GPC SMMU does granule protection checks (GPC) for accesses originating
from the system control block and GIC on RD-Fremont platforms. The GPC
check on this is disabled by the boot firmware. Configure the GPC SMMU
to enable GPC.

The transactions on GPC SMMU should be allowed during boot stages so
don't perform smmuv3_security_init() for this SMMU instance.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: I3400c57fe264582a45c6a26f9dae8c669e8a8047

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feat(rdfremont): update Root registers page offset for SMMUv3

SMMUv3 with RME on RD-Fremont platform variants supports Root and Realm
register pages. The page offset for Root and Realm register page

feat(rdfremont): update Root registers page offset for SMMUv3

SMMUv3 with RME on RD-Fremont platform variants supports Root and Realm
register pages. The page offset for Root and Realm register pages is a
platform configurable option. Update the Root registers page offset for
RD-Fremont platform variants.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ib3df7d7b9e54219d49b4d77a1fc5846096f1c78c

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feat(rdfremont): enable MTE2 if present on the platform

MTE2 is an optional feature that could be part of platforms based on Arm
V8.5 or above. If this feature is implemented on the platform, lower

feat(rdfremont): enable MTE2 if present on the platform

MTE2 is an optional feature that could be part of platforms based on Arm
V8.5 or above. If this feature is implemented on the platform, lower ELs
could potentially access the feature registers leading to EL3 traps.
Therefore, set MTE2 build option to '2' to enable the feature only if
its implemented on the platform.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Idc04b7f3851a2481e4c6bea426a3f09be145b899

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feat(rdfremont): enable SVE for SWD and NS

Enable SVE support for non secure and secure worlds for RD-Fremont
variants.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Signed-off-by: Rohit Mathe

feat(rdfremont): enable SVE for SWD and NS

Enable SVE support for non secure and secure worlds for RD-Fremont
variants.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Idcb309d031a1e10740dd365bb65570f8d2ce3a05

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feat(rdfremont): enable AMU if present on the platform

Set build-option ENABLE_FEAT_AMU to 2 so that AMU is enabled if the
feature is implemented on the platform. This would ensure that lower ELs
co

feat(rdfremont): enable AMU if present on the platform

Set build-option ENABLE_FEAT_AMU to 2 so that AMU is enabled if the
feature is implemented on the platform. This would ensure that lower ELs
could access system registers relevant to AMU registers without causing
a trap to EL3.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I567ac9b0d76b613593d37ea45b4955b423ff5e6c

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feat(rdfremont): enable MPAM if present on the platform

Set build-option ENABLE_FEAT_MPAM to 2 so that access to MPAM related
registers from lower ELs don't trap to EL3.

Signed-off-by: Rohit Mathew

feat(rdfremont): enable MPAM if present on the platform

Set build-option ENABLE_FEAT_MPAM to 2 so that access to MPAM related
registers from lower ELs don't trap to EL3.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I4c5753c415461e5ffc79e371ae00cc6e6dd087f9

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feat(rdfremont): add DRAM pas entries in pas table for multichip

RD-Fremont-Cfg2 supports 8 DRAM banks compared to RD-Fremont and
RD-Fremont-Cfg1, which only support 2. So add PAS entries for
all th

feat(rdfremont): add DRAM pas entries in pas table for multichip

RD-Fremont-Cfg2 supports 8 DRAM banks compared to RD-Fremont and
RD-Fremont-Cfg1, which only support 2. So add PAS entries for
all the DRAM banks in the PAS table for RD-Fremont-Cfg2, ensuring proper
access controls to these regions.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ib09b44569ea088f35529a1c983d3db727d86e262

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feat(rdfremont): add implementation for GPT setup

Since GPT setup has been delegated to the platform, add an
implementation for plat_bl2_gpt_setup in accordance with the
specification for RD-Fremont

feat(rdfremont): add implementation for GPT setup

Since GPT setup has been delegated to the platform, add an
implementation for plat_bl2_gpt_setup in accordance with the
specification for RD-Fremont variants.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I1ff47249ce304f1c188850282d92c64cae463383

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feat(rdfremont): integrate DTS files for RD-Fremont variants

This update incorporates essential device tree (DTS) files for
RD-Fremont variants. The inclusion covers DTS for platform and config
ID,

feat(rdfremont): integrate DTS files for RD-Fremont variants

This update incorporates essential device tree (DTS) files for
RD-Fremont variants. The inclusion covers DTS for platform and config
ID, NT_FW_CONFIG, and TB_FW_CONFIG, enhancing device tree support for
RD-Fremont within the project.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ibf898f963d971fe9b07cfa518244c47a8aced81e

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feat(rdfremont): add support for RD-Fremont-Cfg2

Add board support for RD-Fremont-Cfg2 platform, which is a quad chip
variant of RD-Fremont. Each chip has reduced core count of four CPUs as
compared

feat(rdfremont): add support for RD-Fremont-Cfg2

Add board support for RD-Fremont-Cfg2 platform, which is a quad chip
variant of RD-Fremont. Each chip has reduced core count of four CPUs as
compared to single chip RD-Fremont platform.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I9b79f0eef210afecaa15e381414479027617e44a

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feat(rdfremont): add support for RD-Fremont-Cfg1

Add the required source and header files to support RD-Fremont-Cfg1,
which is a variant of RD-Fremont. RD-Fremont-Cfg1 hosts a smaller mesh
and lower

feat(rdfremont): add support for RD-Fremont-Cfg1

Add the required source and header files to support RD-Fremont-Cfg1,
which is a variant of RD-Fremont. RD-Fremont-Cfg1 hosts a smaller mesh
and lower number of cores when compared with RD-Fremont.

Signed-off-by: Shriram K <shriram.k@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I720b0e76174123c8aab64b39e9468b28614607b9

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feat(rdfremont): add support for RD-Fremont

Add the required source and header files to support RD-Fremont.
Additionally, create a makefile for building the platform.

Co-developed-by: Harry Moulton

feat(rdfremont): add support for RD-Fremont

Add the required source and header files to support RD-Fremont.
Additionally, create a makefile for building the platform.

Co-developed-by: Harry Moulton <harry.moulton@arm.com>
Signed-off-by: Harry Moulton <harry.moulton@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I03b6913b08d488c86a5f4638ef6cd8b0f5c43a9a

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feat(neoverse-rd): add multichip pas entries

RD-Fremont-Cfg2, the quad-chip variant of RD-Fremont supports 8 DRAM
banks compared to RD-Fremont and RD-Fremont-Cfg1, which only support 2.
Therefore, d

feat(neoverse-rd): add multichip pas entries

RD-Fremont-Cfg2, the quad-chip variant of RD-Fremont supports 8 DRAM
banks compared to RD-Fremont and RD-Fremont-Cfg1, which only support 2.
Therefore, define PAS entry mappings for all the DRAM banks, so that
they could be utilized on the multichip variant.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Ief235581c0066a95528235b9821646f864e14d3a

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feat(neoverse-rd): add pas definitions for third gen platforms

Since the GPT setup is now delegated to the platform, each platform
needs to include PAS definitions according to its specifications. T

feat(neoverse-rd): add pas definitions for third gen platforms

Since the GPT setup is now delegated to the platform, each platform
needs to include PAS definitions according to its specifications. This
commit adds PAS definitions specifically tailored for RD-Fremont
variants.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I1a23029a74401fb1faa70bb6c2e66093ed08c45a

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feat(neoverse-rd): add DRAM layout for third gen platforms

Given the differences in memory map of the third generation reference
design platforms, it is necessary to move away from the common DRAM
l

feat(neoverse-rd): add DRAM layout for third gen platforms

Given the differences in memory map of the third generation reference
design platforms, it is necessary to move away from the common DRAM
layout present as part of arm_def.h. Therefore, introduce definitions
and necessary carveouts within DRAM to define a new DRAM layout for
these platforms.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I79af066f41259f147febdc3c00447db5be995799

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