fix(arm): resolve dangling comments around macros

Fix dangling comments around define guards, addressing leftovers from
fe94a21a6 ("fix(arm): move HW_CONFIG relocation into BL31") which
implicitly r

fix(arm): resolve dangling comments around macros

Fix dangling comments around define guards, addressing leftovers from
fe94a21a6 ("fix(arm): move HW_CONFIG relocation into BL31") which
implicitly removed constraints on using HW_CONFIG with RESET_TO_BL2.

Change-Id: I19d61812fed6fa4b668875e5bf4eafd1a8a660f6
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

fix(tc): define status to fix SPM tests

The failure was caused by missing a variable definition, `status`
in the RSE initialisation patch.

Change-Id: I937a39e20fae39f3a6d14fe66af578c166545301
Signe

fix(tc): define status to fix SPM tests

The failure was caused by missing a variable definition, `status`
in the RSE initialisation patch.

Change-Id: I937a39e20fae39f3a6d14fe66af578c166545301
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

show more ...

fix(css): turn the redistributor off on PSCI CPU_OFF

When GICR_WAKER.ProcessorSleep == 1 (i.e. after gicv3_cpuif_disable())
the GIC will assert the WakeRequest signal to try and wake the core up
ins

fix(css): turn the redistributor off on PSCI CPU_OFF

When GICR_WAKER.ProcessorSleep == 1 (i.e. after gicv3_cpuif_disable())
the GIC will assert the WakeRequest signal to try and wake the core up
instead of delivering an interrupt. This is useful when a core is in
some kind of suspend state.

However, when the core is properly off (CPU_OFF), it shouldn't get woken
up in any way other than a CPU_ON call. In the general case interrupts
would be routed away so this doesn't matter. But in case they aren't, we
want the core to stay off.

So turn the redistributor off on CPU_OFF calls. This will prevent the
WakeRequest from being sent.

Change-Id: I7f20591d1c83a4a9639281ef86caa79d6669b536
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

Merge "fix(psa): increase psa-mbedtls heap size for rsa" into integration

fix(tc): eliminate unneeded MbedTLS dependency

The rse_platform_api.h file includes certain MbedTLS headers,
introducing an unnecessary dependency when building the TC
platform with RSE support unco

fix(tc): eliminate unneeded MbedTLS dependency

The rse_platform_api.h file includes certain MbedTLS headers,
introducing an unnecessary dependency when building the TC
platform with RSE support unconditionally.
However, these headers are not required, as the BL31
implementation only initializes RSE communication,
which does not rely on MbedTLS.

Change-Id: If45122aaf158be128f8978422fd870dbb0a0d090
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

Merge "fix(romlib): romlib build without MbedTLS" into integration

Merge "feat(tc): initialize MHU channels with RSE" into integration

Merge "fix(tc): map mem_protect flash region" into integration

Merge changes Ib1b810df,I5492bab5 into integration

* changes:
feat(tc): add dsu pmu node for TC4
feat(tc): enable DSU PMU el1 access for TC4

feat(fpmr): disable FPMR trap

This patch enables support of FEAT_FPMR by enabling access
to FPMR register. It achieves it by setting the EnFPM bit of
SCR_EL3. This feature is currently enabled for N

feat(fpmr): disable FPMR trap

This patch enables support of FEAT_FPMR by enabling access
to FPMR register. It achieves it by setting the EnFPM bit of
SCR_EL3. This feature is currently enabled for NS world only.

Reference:
https://developer.arm.com/documentation/109697/2024_09/
Feature-descriptions/The-Armv9-5-architecture-extension?lang=en

Change-Id: I580c409b9b22f8ead0737502280fb9093a3d5dd2
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

show more ...

fix(psa): increase psa-mbedtls heap size for rsa

The value assigned for the mbedtls heap size for large
rsa keys was too small when PSA_CRYPTO is set to 1,
leading to run-time failures if one was to

fix(psa): increase psa-mbedtls heap size for rsa

The value assigned for the mbedtls heap size for large
rsa keys was too small when PSA_CRYPTO is set to 1,
leading to run-time failures if one was to attempt
to use a large RSA key with PSA_CRYPTO=1.

Change-Id: Id9b2648ae911879f483f1b88301f28694af0721d
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

show more ...

fix(tc): map mem_protect flash region

TC platform was missing this region's mapping in its plat_arm_mmap
structure causing a data abort when trying to access it.

Signed-off-by: Jackson Cooper-Drive

fix(tc): map mem_protect flash region

TC platform was missing this region's mapping in its plat_arm_mmap
structure causing a data abort when trying to access it.

Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I0a6322685f1ee017b0f0cfa795abac0524c13287

show more ...

feat(tc): initialize MHU channels with RSE

Initialize MHU channels between TF-A and RSE, this is a preparation
for later sending messages to RSE.

Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off

feat(tc): initialize MHU channels with RSE

Initialize MHU channels between TF-A and RSE, this is a preparation
for later sending messages to RSE.

Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I66095cafcc1d48249cf957a49dc1dad3059a0010

show more ...

feat(tc): enable DSU PMU el1 access for TC4

Enable DSU PMU EL1 access for TC4 to use DSU PMU using perf
in Linux.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <

feat(tc): enable DSU PMU el1 access for TC4

Enable DSU PMU EL1 access for TC4 to use DSU PMU using perf
in Linux.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I5492bab5c95d60ffaaede4606d8d75c00f988eb6

show more ...

refactor(mbedtls): rename default mbedtls confs

Change the name of these confs to be version agnostic,
we will later use these configs to enforce the mbedtls
minimum version

Change-Id: I1f665c24718

refactor(mbedtls): rename default mbedtls confs

Change the name of these confs to be version agnostic,
we will later use these configs to enforce the mbedtls
minimum version

Change-Id: I1f665c2471877ecc833270c511749ff845046f10
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

show more ...

feat(fvp): build hob library

To produce PHIT HOB list in FVP, add build path for hob library.

Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: I8f4905433bd1cc6f4c9247197b9bd69041f50fd7

fix(romlib): romlib build without MbedTLS

The ROMLIB build currently has a strong dependency on MbedTLS. This
patch has been introduced to remove this dependency, making it more
flexible.

Change-Id

fix(romlib): romlib build without MbedTLS

The ROMLIB build currently has a strong dependency on MbedTLS. This
patch has been introduced to remove this dependency, making it more
flexible.

Change-Id: If8c4cc7cf557687f40b235a4b8f931cfb70943fd
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

Merge "fix(tc): replace vencoder with simple panel for kernel > 6.6" into integration

fix(tc): replace vencoder with simple panel for kernel > 6.6

The component-aware simple encoder has become outdated with the latest
upstream DRM subsystem changes since Linux kernel commit 4cfe5cc02

fix(tc): replace vencoder with simple panel for kernel > 6.6

The component-aware simple encoder has become outdated with the latest
upstream DRM subsystem changes since Linux kernel commit 4cfe5cc02e3f
("drm/arm/komeda: Remove component framework and add a simple encoder")

To address this we introduce a new compilation flag
`TC_DPU_USE_SIMPLE_PANEL` for control panel vs. encoder enablement.
This flag is set when the kernel version is >= 6.6 and 0 when the kernel
version is < 6.6.

We also rename the `vencoder_in` node to `lcd_in` to avoid unnecessary
conditional code for vencoder vs. simple panel enablement.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ibb14a56911cfb406b2181a22cc40db58d8ceaa8d

show more ...

feat(cpus): add support for Alto CPU

Add basic CPU library code to support the Alto CPU.

Change-Id: I45958be99c4a350a32a9e511d3705fb568b97236
Signed-off-by: Igor Podgainõi <igor.podgainoi@arm.com>

feat(tc): fpga: Enable support for loading FIP image to DRAM

This patch enable support for loading FIP image into DRAM rather than
flash drive.

Change-Id: I00d2de7b22e315db7f3e8a835ddd414ab297b554

feat(tc): fpga: Enable support for loading FIP image to DRAM

This patch enable support for loading FIP image into DRAM rather than
flash drive.

Change-Id: I00d2de7b22e315db7f3e8a835ddd414ab297b554
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>

show more ...

feat(tc): allow Android load and Boot From RAM

This commit introduces the below changes:
* Define TC_FPGA_ANDROID_IMG_IN_RAM config variable
* Add phram node in dts.
* Memory configuration for loadi

feat(tc): allow Android load and Boot From RAM

This commit introduces the below changes:
* Define TC_FPGA_ANDROID_IMG_IN_RAM config variable
* Add phram node in dts.
* Memory configuration for loading Android image

Change-Id: I5ec82646cb2993e7b5976e702ebcc8efa51d1128
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>

show more ...

Merge "chore(tc): enable the full 16GB DRAM for TC3 and TC4 as default" into integration

feat(tc): increase SCP BL2 size to support optimization 0

It requires at least 140 KB to support SCP BL2 optimization 0.
Increase the size to 192 KB (0x30000) considering space for growth.

Signed-o

feat(tc): increase SCP BL2 size to support optimization 0

It requires at least 140 KB to support SCP BL2 optimization 0.
Increase the size to 192 KB (0x30000) considering space for growth.

Signed-off-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ib416c89226475d44746a7561dd949a14349c3e4b

show more ...

chore(tc): enable the full 16GB DRAM for TC3 and TC4 as default

Previously we only enabled 8GB unless we were loading the filesystem
from RAM.

Change-Id: Iae60ef460b8cf70f28e62a79db32405daf029e8a
S

chore(tc): enable the full 16GB DRAM for TC3 and TC4 as default

Previously we only enabled 8GB unless we were loading the filesystem
from RAM.

Change-Id: Iae60ef460b8cf70f28e62a79db32405daf029e8a
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>

show more ...