| c58b9a8e | 23-Aug-2022 |
Rupinderjit Singh <rupinderjit.singh@arm.com> |
refactor(cpu): update IP names of Makalu CPU lib
* ASM files are renamed to have public IP names in their filename.
* updated other files to include ASM filename changes.
Signed-off-by: Rupin
refactor(cpu): update IP names of Makalu CPU lib
* ASM files are renamed to have public IP names in their filename.
* updated other files to include ASM filename changes.
Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ie899c512b11fd7c4312e3a808bb6b9d2376cdb8c
show more ...
|
| e2fe267d | 29-Aug-2022 |
Jorge Troncoso <jatron@google.com> |
chore: use tabs for indentation
This patch changes definitions of bl2_mem_params_descs to follow the
TF-A coding style documented at
https://trustedfirmware-a.readthedocs.io/en/latest/process/coding
chore: use tabs for indentation
This patch changes definitions of bl2_mem_params_descs to follow the
TF-A coding style documented at
https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html
Signed-off-by: Jorge Troncoso <jatron@google.com>
Change-Id: I7bd99a50a79499aca0d349e49a3e095e6c5d2f08
show more ...
|
| 5b7bd2af | 09-Aug-2022 |
Shruti Gupta <shruti.gupta@arm.com> |
feat(tsp): increase stack size for tsp
TSP testcases for EL3 SPMC have higher stack usage.
Change-Id: Ib5bfdccc6d0f65174e257f3b0e8b41bcd3c704a6
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com> |
| 3cf080ed | 23-Nov-2021 |
Marc Bonnici <marc.bonnici@arm.com> |
feat(fvp/tsp_manifest): add example manifest for TSP
Add an example manifest for the EL3 SPMC on the FVP Platform
that allows booting the TSP example partition.
Signed-off-by: Marc Bonnici <marc.bo
feat(fvp/tsp_manifest): add example manifest for TSP
Add an example manifest for the EL3 SPMC on the FVP Platform
that allows booting the TSP example partition.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ie7f40328e0313abb5b1a121dfdc22a5f7387587f
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
show more ...
|
| e95abc4c | 14-Jul-2022 |
Salome Thirot <salome.thirot@arm.com> |
fix: make TF-A use provided OpenSSL binary
Currently Tf-A uses whatever openssl binary is on the system to sign
images. However if OPENSSL_DIR is specified in the build flags this can
lead to linkin
fix: make TF-A use provided OpenSSL binary
Currently Tf-A uses whatever openssl binary is on the system to sign
images. However if OPENSSL_DIR is specified in the build flags this can
lead to linking issues as the system binary can end up being linked
against shared libraries provided in OPENSSL_DIR/lib if both binaries
(the system's and the on in OPENSSL_DIR/bin) are the same version.
This patch ensures that the binary used is always the one given by
OPENSSL_DIR to avoid those link issues.
Signed-off-by: Salome Thirot <salome.thirot@arm.com>
Change-Id: Ib534e06ebc8482e4391e376d3791a87968de4a99
show more ...
|
| 9090fe00 | 20-Jun-2022 |
Vishnu Banavath <vishnu.banavath@arm.com> |
(feat)n1sdp: add support for OP-TEE SPMC
These changes are to add support for loading and booting
OP-TEE as SPMC running at SEL1 for N1SDP platform.
Signed-off-by: Vishnu Banavath <vishnu.banavath@
(feat)n1sdp: add support for OP-TEE SPMC
These changes are to add support for loading and booting
OP-TEE as SPMC running at SEL1 for N1SDP platform.
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Change-Id: I0514db646d4868b6f0c56f1ea60495cb3f7364fd
show more ...
|
| 09acc421 | 25-Jul-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(tc): introduce TC2 platform" into integration |
| eebd2c3f | 04-Apr-2022 |
Rupinderjit Singh <rupinderjit.singh@arm.com> |
feat(tc): introduce TC2 platform
Added a platform support to use tc2 specific CPU cores.
Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ib76d440e358e9bd1cf80aec5b8591f7a6e4
feat(tc): introduce TC2 platform
Added a platform support to use tc2 specific CPU cores.
Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ib76d440e358e9bd1cf80aec5b8591f7a6e47ecbd
show more ...
|
| 8597a8cb | 20-Jul-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
fix(tc): tc2 bl1 start address shifted by one page
Change [1] is specific to TC2 model and breaks former TC0/TC1 test
configs.
BL1 start address is 0x0 on TC0/TC1 and 0x1000 from TC2 onwards.
Fix by
fix(tc): tc2 bl1 start address shifted by one page
Change [1] is specific to TC2 model and breaks former TC0/TC1 test
configs.
BL1 start address is 0x0 on TC0/TC1 and 0x1000 from TC2 onwards.
Fix by adding conditional defines depending on TARGET_PLATFORM build
flag.
[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/15917
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I51f77e6a61ca8eaa6871c19cabe9deb1288f5a9d
show more ...
|
| 37d87416 | 18-Jul-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "refactor(fvp): add missing header guard in fvp_critical_data.h" into integration |
| 8dc7645c | 18-Jul-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
refactor(fvp): add missing header guard in fvp_critical_data.h
Change-Id: If7d1a9dd756164c8e31e29d9e36973f1a21fc8b6
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> |
| 9335c28a | 13-Apr-2022 |
Anders Dellien <anders.dellien@arm.com> |
feat(tc): move start address for BL1 to 0x1000
Locate BL1 at 0x1000 to compensate for the MCUBoot
header size.
Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: I30a5ccf8212786479bf
feat(tc): move start address for BL1 to 0x1000
Locate BL1 at 0x1000 to compensate for the MCUBoot
header size.
Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: I30a5ccf8212786479bff8286f3d0abb9dec4b7d0
show more ...
|
| 6f60e94e | 20-Jun-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(arm): add debug logs to show the reason behind skipping firmware config loading
Added debug logs to show the reason behind skipping firmware
configuration loading, and also a few debug stri
refactor(arm): add debug logs to show the reason behind skipping firmware config loading
Added debug logs to show the reason behind skipping firmware
configuration loading, and also a few debug strings were corrected.
Additionally, a panic will be triggered if the configuration sanity
fails.
Change-Id: I6bbd67b72801e178a14cbe677a8831b25a907d0c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| 92eba866 | 07-Jul-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "fix(morello): move BL31 to run from DRAM space" into integration |
| 94df8da3 | 25-Jan-2022 |
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> |
feat(sgi): bump bl1 rw size
Increase BL1 RW size by 16 KiB to accommodate for future development.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I21626a97de
feat(sgi): bump bl1 rw size
Increase BL1 RW size by 16 KiB to accommodate for future development.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I21626a97de4a6c98c25b93b9f79e16325c6e4349
show more ...
|
| 1d74b4bb | 25-Jan-2022 |
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> |
refactor(sgi): rewrite address space size definitions
The value of the macro CSS_SGI_REMOTE_CHIP_MEM_OFFSET can be different
across all the Neoverse reference design platforms. This value depends
on
refactor(sgi): rewrite address space size definitions
The value of the macro CSS_SGI_REMOTE_CHIP_MEM_OFFSET can be different
across all the Neoverse reference design platforms. This value depends
on the number of address bits used per chip. So let all platforms define
CSS_SGI_ADDR_BITS_PER_CHIP which specifies the number of address bits
used per chip.
In addition to this, reuse the definition of CSS_SGI_ADDR_BITS_PER_CHIP
for single chip platforms and CSS_SGI_REMOTE_CHIP_MEM_OFFSET for multi-
chip platforms to determine the maximum address space size. Also,
increase the RD-N2 multi-chip address space per chip from 4TB to 64TB.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: If5e69ec26c2389304c71911729d4addbdf8b2686
show more ...
|
| 05330a49 | 23-Jun-2022 |
Manoj Kumar <manoj.kumar3@arm.com> |
fix(morello): move BL31 to run from DRAM space
The EL3 runtime firmware has been running from internal trusted
SRAM space on the Morello platform. Due to unavailability of tag
support for the intern
fix(morello): move BL31 to run from DRAM space
The EL3 runtime firmware has been running from internal trusted
SRAM space on the Morello platform. Due to unavailability of tag
support for the internal trusted SRAM this becomes a problem if
we enable capability pointers in BL31.
To support capability pointers in BL31 it has to be run from the
main DDR memory space. This patch updates the Morello platform
configuration such that BL31 is loaded and run from DDR space.
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Change-Id: I16d4d757fb6f58c364f5133236d50fc06845e0b4
show more ...
|
| 717daadc | 05-Jul-2022 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "jas/rmm-el3-ifc" into integration
* changes:
docs(rmmd): document EL3-RMM Interfaces
feat(rmmd): add support to create a boot manifest
fix(rme): use RMM shared buffer
Merge changes from topic "jas/rmm-el3-ifc" into integration
* changes:
docs(rmmd): document EL3-RMM Interfaces
feat(rmmd): add support to create a boot manifest
fix(rme): use RMM shared buffer for attest SMCs
feat(rmmd): add support for RMM Boot interface
show more ...
|
| 1ae014dd | 05-Jul-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "feat(arm): forbid running RME-enlightened BL31 from DRAM" into integration |
| 1d0ca40e | 25-Apr-2022 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
feat(rmmd): add support to create a boot manifest
This patch also adds an initial RMM Boot Manifest (v0.1) for fvp
platform.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Ch
feat(rmmd): add support to create a boot manifest
This patch also adds an initial RMM Boot Manifest (v0.1) for fvp
platform.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I1374f8f9cb207028f1820953cd2a5cf6d6c3b948
show more ...
|
| dc65ae46 | 13-Apr-2022 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
fix(rme): use RMM shared buffer for attest SMCs
Use the RMM shared buffer to attestation token and signing key SMCs.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id:
fix(rme): use RMM shared buffer for attest SMCs
Use the RMM shared buffer to attestation token and signing key SMCs.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I313838b26d3d9334fb0fe8cd4b229a326440d2f4
show more ...
|
| 8c980a4a | 24-Nov-2021 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
feat(rmmd): add support for RMM Boot interface
This patch adds the infrastructure needed to pass boot arguments from
EL3 to RMM and allocates a shared buffer between both worlds that can
be used, am
feat(rmmd): add support for RMM Boot interface
This patch adds the infrastructure needed to pass boot arguments from
EL3 to RMM and allocates a shared buffer between both worlds that can
be used, among others, to pass a boot manifest to RMM. The buffer is
composed a single memory page be used by a later EL3 <-> RMM interface
by all CPUs.
The RMM boot manifest is not implemented by this patch.
In addition to that, this patch also enables support for RMM when
RESET_TO_BL31 is enabled.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I855cd4758ee3843eadd9fb482d70a6d18954d82a
show more ...
|
| 1164a59c | 04-Jul-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
feat(arm): forbid running RME-enlightened BL31 from DRAM
According to Arm CCA security model [1],
"Root world firmware, including Monitor, is the most trusted CCA
component on application PE. It en
feat(arm): forbid running RME-enlightened BL31 from DRAM
According to Arm CCA security model [1],
"Root world firmware, including Monitor, is the most trusted CCA
component on application PE. It enforces CCA security guarantees for
not just Realm world, but also for Secure world and for itself.
It is expected to be small enough to feasibly fit in on-chip memory,
and typically needs to be available early in the boot process when
only on-chip memory is available."
For these reasons, it is expected that "monitor code executes entirely
from on-chip memory."
This precludes usage of ARM_BL31_IN_DRAM for RME-enlightened firmware.
[1] Arm DEN0096 A.a, section 7.3 "Use of external memory by CCA".
Change-Id: I752eb45f1e6ffddc7a6f53aadcc92a3e71c1759f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
show more ...
|
| 2d8e80c2 | 30-Jun-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topics "binary-format-sp", "od/meas-boot-spmc" into integration
* changes:
feat(spm): add tpm event log node to spmc manifest
fix(measured-boot): add SP entries to event_log_m
Merge changes from topics "binary-format-sp", "od/meas-boot-spmc" into integration
* changes:
feat(spm): add tpm event log node to spmc manifest
fix(measured-boot): add SP entries to event_log_metadata
show more ...
|
| 02450800 | 27-Jun-2022 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "mb_hash" into integration
* changes:
refactor(imx): update config of mbedtls support
refactor(qemu): update configuring mbedtls support
refactor(measured-boot): mb al
Merge changes from topic "mb_hash" into integration
* changes:
refactor(imx): update config of mbedtls support
refactor(qemu): update configuring mbedtls support
refactor(measured-boot): mb algorithm selection
show more ...
|