| 445130b1 | 11-Apr-2022 |
David Vincze <david.vincze@arm.com> |
feat(tc): add RSS-AP message size macro
Define the RSS_COMMS_PAYLOAD_MAX_SIZE macro. Its value is platform
specific and gives the largest message size which are exchanged
on the TC2 platform between
feat(tc): add RSS-AP message size macro
Define the RSS_COMMS_PAYLOAD_MAX_SIZE macro. Its value is platform
specific and gives the largest message size which are exchanged
on the TC2 platform between RSS and AP.
Change-Id: Id831c282dc9a39755b82befead1a81767e217215
Signed-off-by: David Vincze <david.vincze@arm.com>
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
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| 6299c3a0 | 13-Apr-2022 |
David Vincze <david.vincze@arm.com> |
feat(tc): add MHU addresses for AP-RSS comms on TC2
Change-Id: I600485ca83f91378d07cac6cee484bc4a1bf2a9c
Signed-off-by: David Vincze <david.vincze@arm.com> |
| d5f225d9 | 04-Jul-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(fvp): add plat API to validate that passed region is non-secure
Added a platform function to check passed region is within
the Non-Secure region of DRAM.
Signed-off-by: Manish V Badarkhe <Mani
feat(fvp): add plat API to validate that passed region is non-secure
Added a platform function to check passed region is within
the Non-Secure region of DRAM.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ie5808fa6a1b6e6bc99f4185fa8acc52af0d5f14d
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| 586f60cc | 12-Jul-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(fvp): add plat API to set and get the DRTM error
Added a platform function to set and get DRTM error.
Also, added a platform function to reset the system.
Signed-off-by: Manish V Badarkhe <Man
feat(fvp): add plat API to set and get the DRTM error
Added a platform function to set and get DRTM error.
Also, added a platform function to reset the system.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I471f2387f8c78b21a06af063a6fa02cda3646557
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| 40814266 | 17-Jun-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(drtm): add Event Log driver support for DRTM
Added Event Log driver support for DRTM. This driver
is responsible for the doing the hash measurement of
various DRTM components as per [1], and pu
feat(drtm): add Event Log driver support for DRTM
Added Event Log driver support for DRTM. This driver
is responsible for the doing the hash measurement of
various DRTM components as per [1], and putting these
measurements in the Event Log buffer.
[1]: https://developer.arm.com/documentation/den0113/a, section 3.16
Change-Id: I9892c313cf6640b82e261738116fe00f7975ee12
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 2a1cdee4 | 11-Mar-2022 |
johpow01 <john.powell@arm.com> |
feat(drtm): add platform functions for DRTM
Added platform hooks to retrieve DRTM features and
address map.
Additionally, implemented these hooks for the FVP platform.
Signed-off-by: John Powell <j
feat(drtm): add platform functions for DRTM
Added platform hooks to retrieve DRTM features and
address map.
Additionally, implemented these hooks for the FVP platform.
Signed-off-by: John Powell <john.powell@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I5621cc9807ffff8139ae8876250147f7b2c76759
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| c9bd1bac | 25-Feb-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
feat(fvp): add crypto support in BL31
DRTM implementation needs crypto support in BL31 to calculate
hash of various DRTM components
Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Change
feat(fvp): add crypto support in BL31
DRTM implementation needs crypto support in BL31 to calculate
hash of various DRTM components
Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Change-Id: I659ce8e54550946db253d23f150cca8b2fa7b880
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| 8a8dace5 | 23-Feb-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
feat(fvp): increase MAX_XLAT_TABLES entries for DRTM support
DRTM implementation maps the DLME data region provided by the
DCE-preamble in BL31, hence increased MAX_XLAT_TABLES entries
count.
Signe
feat(fvp): increase MAX_XLAT_TABLES entries for DRTM support
DRTM implementation maps the DLME data region provided by the
DCE-preamble in BL31, hence increased MAX_XLAT_TABLES entries
count.
Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Signed-off-by: Lucian Paul-Trifu <lucian.paultrifu@gmail.com>
Change-Id: I5f0ac69e009c4f81d3590fdb1f4c0a7f73c5c99d
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| 44df105f | 23-Feb-2022 |
Lucian Paul-Trifu <lucian.paultrifu@gmail.com> |
feat(fvp): increase BL31's stack size for DRTM support
The stack size of BL31 has been increased to accommodate the
introduction of mbedTLS support for DRTM.
Signed-off-by: Manish V Badarkhe <manis
feat(fvp): increase BL31's stack size for DRTM support
The stack size of BL31 has been increased to accommodate the
introduction of mbedTLS support for DRTM.
Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Signed-off-by: Lucian Paul-Trifu <lucian.paultrifu@gmail.com>
Change-Id: Id0beacf4df553af4ecbe714af20e71604ccfed59
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| d72c486b | 22-Jun-2022 |
Lucian Paul-Trifu <lucian.paultrifu@gmail.com> |
feat(fvp): add platform hooks for DRTM DMA protection
Added necessary platform hooks for DRTM DMA protection.
These calls will be used by the subsequent DRTM implementation
patches.
DRTM platform AP
feat(fvp): add platform hooks for DRTM DMA protection
Added necessary platform hooks for DRTM DMA protection.
These calls will be used by the subsequent DRTM implementation
patches.
DRTM platform API declarations have been listed down in a
separate header file.
Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Signed-off-by: Lucian Paul-Trifu <lucian.paultrifu@gmail.com>
Change-Id: Ib9726d1d3570800241bde702ee7006a64f1739ec
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| afc9b23b | 05-Oct-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(fvp): support building RSS comms driver" into integration |
| b139f1cf | 15-Aug-2022 |
Mikael Olsson <mikael.olsson@arm.com> |
feat(ethos-n)!: add support for SMMU streams
The Arm(R) Ethos(TM)-N NPU driver now supports configuring the SMMU
streams that the NPU shall use and will therefore no longer delegate
access to these
feat(ethos-n)!: add support for SMMU streams
The Arm(R) Ethos(TM)-N NPU driver now supports configuring the SMMU
streams that the NPU shall use and will therefore no longer delegate
access to these registers to the non-secure world. In order for the
driver to support this, the device tree parsing has been updated to
support parsing the allocators used by the NPU and what SMMU stream that
is associated with each allocator.
To keep track of what NPU device each allocator is associated with, the
resulting config from the device tree parsing will now group the NPU
cores and allocators into their respective NPU device.
The SMC API has been changed to allow the caller to specify what
allocator the NPU shall be configured to use and the API version has
been bumped to indicate this change.
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I6ac43819133138614e3f55a014e93466fe3d5277
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| 29e6fc5c | 31-Aug-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
feat(fvp): support building RSS comms driver
On one hand, there is currently no upstream platform supporting the
RSS. On the other hand, we are gradually introducing driver code for
RSS. Even though
feat(fvp): support building RSS comms driver
On one hand, there is currently no upstream platform supporting the
RSS. On the other hand, we are gradually introducing driver code for
RSS. Even though we cannot test this code in the TF-A CI right now, we
can at least build it to make sure no build regressions are introduced
as we continue development.
This patch adds support for overriding PLAT_RSS_NOT_SUPPORTED build
flag (which defaults to 1 on the Base AEM FVP) from the command
line. This allows introducing an ad-hoc CI build config with
PLAT_RSS_NOT_SUPPORTED=0, which will correctly pull in the RSS and MHU
source files. Of course, the resulting firmware will not be
functional.
Change-Id: I2b0e8dd03bf301e7063dd4734ea5266b73265be1
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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| 91890b7a | 21-Sep-2022 |
Joel Goddard <joel.goddard@arm.com> |
refactor(sgi): rename RD-Edmunds to RD-V2
Neoverse Reference Design platform RD-Edmunds has been renamed to RD-V2
and so all corresponding references have been changed.
Signed-off-by: Joel Goddard
refactor(sgi): rename RD-Edmunds to RD-V2
Neoverse Reference Design platform RD-Edmunds has been renamed to RD-V2
and so all corresponding references have been changed.
Signed-off-by: Joel Goddard <joel.goddard@arm.com>
Change-Id: I134f125f8ce9ec2f42988ecd742de307da936f2b
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| bd063a73 | 21-Sep-2022 |
Joel Goddard <joel.goddard@arm.com> |
refactor(cpu): use the updated IP name for Demeter CPU
Neoverse Demeter CPU has been renamed to Neoverse V2 CPU.
Correspondingly, update the CPU library, file names and other
references to use the u
refactor(cpu): use the updated IP name for Demeter CPU
Neoverse Demeter CPU has been renamed to Neoverse V2 CPU.
Correspondingly, update the CPU library, file names and other
references to use the updated IP name.
Signed-off-by: Joel Goddard <joel.goddard@arm.com>
Change-Id: Ia4bf45bf47807c06f4c966861230faea420d088f
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| 364b4cdd | 19-Sep-2022 |
Mate Toth-Pal <mate.toth-pal@arm.com> |
fix(rme): update FVP platform token
Update test CCA Platform token in fvp_plat_attest_token.c to be
up-to-date with RMM spec Beta0.
Change-Id: I0f5e2ac1149eb6f7a93a997682f41d90e109a049
Signed-off-b
fix(rme): update FVP platform token
Update test CCA Platform token in fvp_plat_attest_token.c to be
up-to-date with RMM spec Beta0.
Change-Id: I0f5e2ac1149eb6f7a93a997682f41d90e109a049
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
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| 2aaed860 | 23-Sep-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "refactor(libc): clean up dependencies in libc" into integration |
| a371327b | 08-Jul-2022 |
Rohit Mathew <rohit.mathew@arm.com> |
feat(sgi): remove override for `ARM_BL31_IN_DRAM` build-option
RD-N2* variants of Neoverse reference design platforms could be
configured to boot from SRAM or DRAM. Having ARM_BL31_IN_DRAM set to 1
feat(sgi): remove override for `ARM_BL31_IN_DRAM` build-option
RD-N2* variants of Neoverse reference design platforms could be
configured to boot from SRAM or DRAM. Having ARM_BL31_IN_DRAM set to 1
within the common makefile would deter these platforms from having this
flexibility. Remove the default override configuration for
`ARM_BL31_IN_DRAM`.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I8d79969c003a984675cbe705de890b51a1f7f4ea
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| 8fd820ff | 08-Jul-2022 |
Rohit Mathew <rohit.mathew@arm.com> |
feat(sgi): configure SRAM and BL31 size for sgi platform
Update SRAM size for Neoverse reference design platforms from 256KB to
512KB. This is required to place and execute BL31 image from the
on-ch
feat(sgi): configure SRAM and BL31 size for sgi platform
Update SRAM size for Neoverse reference design platforms from 256KB to
512KB. This is required to place and execute BL31 image from the
on-chip SRAM. Additionally, revise BL31 image size to accommodate
larger BL31 images of multi-chip platforms.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I11c2672a1089f24a9fafcf6555b8e1d52032cfde
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| 885e2683 | 12-Sep-2022 |
Claus Pedersen <claustbp@google.com> |
refactor(libc): clean up dependencies in libc
- Removing platform dependencies from libc modules.
- Replacing panicking with actual error handling.
- Debug macros are included indirectly from assert
refactor(libc): clean up dependencies in libc
- Removing platform dependencies from libc modules.
- Replacing panicking with actual error handling.
- Debug macros are included indirectly from assert.h. Removing
"platform_def.h" from assert.h and adding "common/debug.h"
where the macros are used.
- Removing hack for fixing PLAT_LOG_LEVEL_ASSERT to 40.
Instead removing assert with expression, as this
does not provide additional information.
Signed-off-by: Claus Pedersen <claustbp@google.com>
Change-Id: Icc201ea7b63c1277e423c1cfd13fd6816c2bc568
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| 18884c00 | 27-Jul-2022 |
Pranav Madhu <pranav.madhu@arm.com> |
feat(sgi): enable css implementation of warm reset
Enable the CSS implementation of the warm reset for the rdn2 platform.
In addition to these changes, fix coding style issues that are not
directl
feat(sgi): enable css implementation of warm reset
Enable the CSS implementation of the warm reset for the rdn2 platform.
In addition to these changes, fix coding style issues that are not
directly related to the code being introduced in this patch.
Change-Id: I75128d8bbcccbc26cf1e904691c7ef71349c622f
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
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| 14a28923 | 22-Jul-2022 |
Pranav Madhu <pranav.madhu@arm.com> |
feat(scmi): send powerdown request to online secondary cpus
To initiate a reset or reboot, the nonsecure OS invokes the PSCI
SYSTEM_RESET function from any one core. As per the PSCI specification,
i
feat(scmi): send powerdown request to online secondary cpus
To initiate a reset or reboot, the nonsecure OS invokes the PSCI
SYSTEM_RESET function from any one core. As per the PSCI specification,
it is the responsibility of firmware to implement the system view of
the reset or reboot operation. For the platforms supported by CSS,
trigger the reset/reboot operation by sending an SGI to rest all CPUs
which are online. The CPUs respond to this interrupt by initiating its
powerdown sequence.
In addition to these changes, fix coding style issues that are not
directly related to the code being introduced in this patch.
Change-Id: I547253ee28ef7eefa78180d016893671a406bbfa
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
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| f1fe1440 | 27-Jul-2022 |
Pranav Madhu <pranav.madhu@arm.com> |
feat(plat/arm/css): add interrupt handler for reboot request
Add platform specific interrupt handler for handling the reboot of
all CPU's. On shutdown/reboot, only one CPU invoke PSCI and enter into
feat(plat/arm/css): add interrupt handler for reboot request
Add platform specific interrupt handler for handling the reboot of
all CPU's. On shutdown/reboot, only one CPU invoke PSCI and enter into
trusted firmware. The CPU which entered trusted firmware signals the
rest of the cores which are online using SGI to initiate power down
sequence. On receiving the SGI, the handler will power down the
GIC redistributor interface of the respective core, configure the power
control register and power down the CPU by executing wfi.
In addition to these changes, fix coding style issues that are not
directly related to the code being introduced in this patch.
Change-Id: I4917dfdc47be5ce7367bee629486a6344cdd706f
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
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| 158ed580 | 27-Jul-2022 |
Pranav Madhu <pranav.madhu@arm.com> |
feat(plat/arm/css): add per-cpu power down support for warm reset
Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SY
feat(plat/arm/css): add per-cpu power down support for warm reset
Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SYSTEM_RESET
request. This will be used on CSS platform that require all the CPUs to
execute the CPU specific power down sequence to complete a warm reboot
sequence in which only the CPUs are power cycled.
Change-Id: I80da0f6c3cd0c5c442c82239ba1e1f773821a7f5
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
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| 4a81e91f | 20-Jun-2022 |
Himanshu Sharma <Himanshu.Sharma@arm.com> |
fix(n1sdp): mapping Run-time UART to IOFPGA UART0
Currently the Run-time UART is mapped to AP UART1 which is internally
routed to MCP UART1, so unsharing it from AP UART1 and mapping it to
IOFPGA UA
fix(n1sdp): mapping Run-time UART to IOFPGA UART0
Currently the Run-time UART is mapped to AP UART1 which is internally
routed to MCP UART1, so unsharing it from AP UART1 and mapping it to
IOFPGA UART0 for exclusiveness among the usage of the UARTs.
Signed-off-by: Himanshu Sharma <Himanshu.Sharma@arm.com>
Change-Id: I366740a971a880decf0d373e9055e7ebda5df53a
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