plat/sgi: improve macros defining cper buffer memory region

Remove the 'ARM_' prefix from the macros defining the CPER buffer memory
and replace it with 'CSS_SGI_' prefix. These macros are applicabl

plat/sgi: improve macros defining cper buffer memory region

Remove the 'ARM_' prefix from the macros defining the CPER buffer memory
and replace it with 'CSS_SGI_' prefix. These macros are applicable only
for platforms supported within plat/sgi. In addition to this, ensure
that these macros are defined only if the RAS_EXTENSION build option is
enabled.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I44df42cded18d9d3a4cb13e5c990e9ab3194daee

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plat/sgi: refactor DMC-620 error handling SMC function id

The macros defining the SMC function ids for DMC-620 error handling are
listed in the sgi_base_platform_def.h header file. But these macros

plat/sgi: refactor DMC-620 error handling SMC function id

The macros defining the SMC function ids for DMC-620 error handling are
listed in the sgi_base_platform_def.h header file. But these macros are
not applicable for all platforms supported under plat/sgi. So move these
macro definitions to sgi_ras.c file in which these are consumed. While
at it, remove the AArch32 and error injection function ids as these are
unused.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I249b54bf4c1b1694188a1e3b297345b942f16bc9

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plat/sgi: refactor SDEI specific macros

The macros specific to SDEI defined in the sgi_base_platform_def.h are
not applicable for all the platforms supported by plat/sgi. So refactor
the SDEI specif

plat/sgi: refactor SDEI specific macros

The macros specific to SDEI defined in the sgi_base_platform_def.h are
not applicable for all the platforms supported by plat/sgi. So refactor
the SDEI specific macros into a new header file and include this file on
only on platforms it is applicable on.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I0cb7125334f02a21cae1837cdfd765c16ab50bf5

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plat/arm/css: rename rd_n1e1_edge_scmi_plat_info array

Rename rd_n1e1_edge_scmi_plat_info array to plat_rd_scmi_info as the
same array is used to provide SCMI platform info across mulitple RD
platfo

plat/arm/css: rename rd_n1e1_edge_scmi_plat_info array

Rename rd_n1e1_edge_scmi_plat_info array to plat_rd_scmi_info as the
same array is used to provide SCMI platform info across mulitple RD
platforms and is not resitricted to only RD-N1 and RD-E1 platforms.

Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I42ba33e0afa3003c731ce513c6a5754b602ec01f

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plat/arm/sgi: allow all PSCI callbacks on RD-V1

Some of the PSCI platform callbacks were restricted on RD-V1 platform
because the idle was not functional. Now that it is functional, remove
all the r

plat/arm/sgi: allow all PSCI callbacks on RD-V1

Some of the PSCI platform callbacks were restricted on RD-V1 platform
because the idle was not functional. Now that it is functional, remove
all the restrictions on the use PSCI platform callbacks.

Change-Id: I4cb97cb54de7ee166c30f28df8fea653b6b425c7
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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Merge "plat/arm: css: Turn ON/OFF redistributor in sync with GIC CPU interface ON/OFF" into integration

plat/arm/css/sgi: Fix assert expression issue

Violation of MISRA-C Rule 14.4

Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: I44ef50dadb54fb056a91f3de962b6e63ba6d7ac4

plat/arm/css/sgi: Fix bl32 receive event - 0xC4000061 issue

The issue is that, when interrupt is triggered and RAS handler
is entered, after interrupt handler finishes, TF-A will re-enter
bl32 and t

plat/arm/css/sgi: Fix bl32 receive event - 0xC4000061 issue

The issue is that, when interrupt is triggered and RAS handler
is entered, after interrupt handler finishes, TF-A will re-enter
bl32 and then crash.
sdei_dispatch_event() may return failing result in some cases,
for example kernel may not have registered a handler or RAS event
may happen early during boot. We restore the NS context when
sdei_dispatch_event() returns failing result.

error log :
Received delegated event
X0 : 0xC4000061
X1 : 0x0
X2 : 0x0
X3 : 0x0
Received event - 0xC4000061 on cpu 0
UnRecognized Event - 0xC4000061
Failed delegated event 0xC4000061, Status Invalid Parameter
Unhandled Exception in EL3.
x30 = 0x000000000401f700
x0 = 0xfffffffffffffffe
x1 = 0xfffffffffffffffe
x2 = 0x00000000600003c0

Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: I9802e9a32eee0ac3b5a8bcc0362d0b0e3b71dc9f

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plat/arm: css: Turn ON/OFF redistributor in sync with GIC CPU interface ON/OFF

Turn ON/OFF GIC redistributor in sync with GIC CPU interface ON/OFF.

Issue :
The Linux prompt hangs when all the cores

plat/arm: css: Turn ON/OFF redistributor in sync with GIC CPU interface ON/OFF

Turn ON/OFF GIC redistributor in sync with GIC CPU interface ON/OFF.

Issue :
The Linux prompt hangs when all the cores in a cluster are turned OFF
and we try to turn ON a core in that cluster. Previously when TF-A turns
ON a core, TF-A first turns ON the redistributor followed by the core.
This did not match the flow when turning OFF a core, as TF-A did not
turn OFF redistributor when the corresponding core[s] are disabled.
This hang is resolved by disabling redistributor as cores are disabled,
keeping them in sync.

Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com>
Change-Id: Ifd04fdcfd47b45e00f874f15b098471883d023f0

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plat/arm: rename rddaniel to rdv1

Reference Design platform RD-Daniel has been renamed to RD-V1.
Correspondingly, remove all uses of 'rddaniel' and replace it with
'rdv1' where appropriate.

Signed-

plat/arm: rename rddaniel to rdv1

Reference Design platform RD-Daniel has been renamed to RD-V1.
Correspondingly, remove all uses of 'rddaniel' and replace it with
'rdv1' where appropriate.

Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I1702bab39c501f8c0a09df131cb2394d54c83bcf

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plat/arm/sgi: adapt to changes in memory map

Upcoming RD platforms will have an updated memory map for the various
pheripherals on the system. So, for the newer platforms, handle the
memory mapping

plat/arm/sgi: adapt to changes in memory map

Upcoming RD platforms will have an updated memory map for the various
pheripherals on the system. So, for the newer platforms, handle the
memory mapping and other platform specific functionality separately
from the existing platforms.

Change-Id: Iab1355a4c8ea1f6db4f79fcdd6eed907903b6a18
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

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plat/arm/sgi: add platform id value for rdn2 platform

In preparation for adding the board support for RD-N2 platform, add
macros to define the platform id and the corresponding SCMI platform
info fo

plat/arm/sgi: add platform id value for rdn2 platform

In preparation for adding the board support for RD-N2 platform, add
macros to define the platform id and the corresponding SCMI platform
info for the RD-N2 platform.

Change-Id: Ie764ae618732b39e316f7ed080421f5d79adab21
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

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plat/arm/sgi: platform definitions for upcoming platforms

Upcoming RD platforms have changes in the SOC address map from that
of the existing platforms. As a prepartory step to add support for the
u

plat/arm/sgi: platform definitions for upcoming platforms

Upcoming RD platforms have changes in the SOC address map from that
of the existing platforms. As a prepartory step to add support for the
upcoming platforms, create platform definitions for those platforms.

Change-Id: Ic5df9fed02c44e65ec260bbb5efc1b8dbd919a56
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

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plat/arm/sgi: refactor header file inclusions

Upcoming RD platforms have deviations in various definitions of
platform macros from that of the exisiting platforms. In preparation
for adding support

plat/arm/sgi: refactor header file inclusions

Upcoming RD platforms have deviations in various definitions of
platform macros from that of the exisiting platforms. In preparation
for adding support for those upcoming RD platforms, refactor the
header file inclusion to allow newer platforms to use a different
set of platform macros.

Change-Id: Ic80283ddadafaa7f766f300652cb0d4e507efdb6
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

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plat/arm/sgi: refactor the inclusion of memory mapping

Upcoming RD platforms have a different memory map from those of the
existing platforms. So make the build of the existing mmap entries to be
us

plat/arm/sgi: refactor the inclusion of memory mapping

Upcoming RD platforms have a different memory map from those of the
existing platforms. So make the build of the existing mmap entries to be
usable only for existing platforms and let upcoming platforms define
a different set of mmap entries.

Change-Id: Id1ef0293efe8749c78a99237e78d32573c7233aa
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

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plat/arm/css/sgi: Map flash used for mem_protect

The SGI platform defines the macro PLAT_ARM_MEM_PROT_ADDR which
indicates that the platform has mitigation for cold reboot attacks.

However, the fla

plat/arm/css/sgi: Map flash used for mem_protect

The SGI platform defines the macro PLAT_ARM_MEM_PROT_ADDR which
indicates that the platform has mitigation for cold reboot attacks.

However, the flash memory used for the mem_protect region was not
mapped. This results in a crash when an OS calls PSCI MEM_PROTECT.

To fix this map the flash region used for mem_protect.

Change-Id: Ia494f924ecfe2ce835c045689ba8f942bf0941f4
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>

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spm-mm: fix MISRA C-2012 Rule 2.3 spm_mm_boot_info_t defined but never used.

Following merge of patchset [1] the spm_mm_boot_info_t structure is
included in few platform files unconditionally even w

spm-mm: fix MISRA C-2012 Rule 2.3 spm_mm_boot_info_t defined but never used.

Following merge of patchset [1] the spm_mm_boot_info_t structure is
included in few platform files unconditionally even when SPM_MM option
is disabled.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/2647

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I68bc034c9348b5d9bcfd2e5217b781df5ad1b369

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plat/arm: sgm: Use consistent name for tb fw config node

Renamed node for trusted boot fw config from 'plat_arm_bl2' to
'tb_fw-config'.

Change-Id: I2e16b6f4d272292ec1855daafd014e851436dd9b
Signed-o

plat/arm: sgm: Use consistent name for tb fw config node

Renamed node for trusted boot fw config from 'plat_arm_bl2' to
'tb_fw-config'.

Change-Id: I2e16b6f4d272292ec1855daafd014e851436dd9b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fconf: Clean confused naming between TB_FW and FW_CONFIG

Cleaned up confused naming between TB_FW and FW_CONFIG.

Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Signed-off-by: Manish V B

fconf: Clean confused naming between TB_FW and FW_CONFIG

Cleaned up confused naming between TB_FW and FW_CONFIG.

Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I9e9f6e6ca076d38fee0388f97d370431ae067f08

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plat/arm: Rentroduce tb_fw_config device tree

Moved BL2 configuration nodes from fw_config to newly
created tb_fw_config device tree.

fw_config device tree's main usage is to hold properties shared

plat/arm: Rentroduce tb_fw_config device tree

Moved BL2 configuration nodes from fw_config to newly
created tb_fw_config device tree.

fw_config device tree's main usage is to hold properties shared
across all BLx images.
An example is the "dtb-registry" node, which contains the
information about the other device tree configurations
(load-address, size).

Also, Updated load-address of tb_fw_config which is now located
after fw_config in SRAM.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ic398c86a4d822dacd55b5e25fd41d4fe3888d79a

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GICv3: GIC-600: Detect GIC-600 at runtime

The only difference between GIC-500 and GIC-600 relevant to TF-A is the
differing power management sequence.
A certain GIC implementation is detectable at r

GICv3: GIC-600: Detect GIC-600 at runtime

The only difference between GIC-500 and GIC-600 relevant to TF-A is the
differing power management sequence.
A certain GIC implementation is detectable at runtime, for instance by
checking the IIDR register. Let's add that test before initiating the
GIC-600 specific sequence, so the code can be used on both GIC-600 and
GIC-500 chips alike, without deciding on a GIC chip at compile time.

This means that the GIC-500 "driver" is now redundant. To allow minimal
platform support, add a switch to disable GIC-600 support.

Change-Id: I17ea97d9fb05874772ebaa13e6678b4ba3415557
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "Provide a hint to power controller for DSU cluster power down" into integration

juno/sgm: Align SCP_BL2 to page boundary

This commit fixes an assertion that was triggering in certain contexts:

ERROR: mmap_add_region_check() failed. error -22
ASSERT: lib/xlat_tables_v2/

juno/sgm: Align SCP_BL2 to page boundary

This commit fixes an assertion that was triggering in certain contexts:

ERROR: mmap_add_region_check() failed. error -22
ASSERT: lib/xlat_tables_v2/xlat_tables_core.c:790

Change-Id: Ia55b3fb4f496c8cd791ea6093d122edae0a7e92a
Signed-off-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Provide a hint to power controller for DSU cluster power down

By writing 0 to CLUSTERPWRDN DSU register bit 0, we send an
advisory to the power controller that cluster power is not required
when all

Provide a hint to power controller for DSU cluster power down

By writing 0 to CLUSTERPWRDN DSU register bit 0, we send an
advisory to the power controller that cluster power is not required
when all cores are powered down.

The AArch32 CLUSTERPWRDN register is architecturally mapped to the
AArch64 CLUSTERPWRDN_EL1 register

Change-Id: Ie6e67c1c7d811fa25c51e2e405ca7f59bd20c81b
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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plat/arm/sgi: update mmap and xlat count

A single chip platform requires five mmap entries and a corresponding
number of translation tables. For every additional chip in the system,
three additional

plat/arm/sgi: update mmap and xlat count

A single chip platform requires five mmap entries and a corresponding
number of translation tables. For every additional chip in the system,
three additional mmap entries are required to map the shared SRAM and
the IO regions. A corresponding number of additional translation
tables are required as well.

Change-Id: I1332a1305f2af62181387cf36954f6fb0e6f11ed
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

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