1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <drivers/arm/css/css_scp.h> 14 #include <lib/cassert.h> 15 #include <plat/arm/common/plat_arm.h> 16 #include <plat/arm/css/common/css_pm.h> 17 18 /* Allow CSS platforms to override `plat_arm_psci_pm_ops` */ 19 #pragma weak plat_arm_psci_pm_ops 20 21 #if ARM_RECOM_STATE_ID_ENC 22 /* 23 * The table storing the valid idle power states. Ensure that the 24 * array entries are populated in ascending order of state-id to 25 * enable us to use binary search during power state validation. 26 * The table must be terminated by a NULL entry. 27 */ 28 const unsigned int arm_pm_idle_states[] = { 29 /* State-id - 0x001 */ 30 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN, 31 ARM_LOCAL_STATE_RET, ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), 32 /* State-id - 0x002 */ 33 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN, 34 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), 35 /* State-id - 0x022 */ 36 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, 37 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), 38 #if PLAT_MAX_PWR_LVL > ARM_PWR_LVL1 39 /* State-id - 0x222 */ 40 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 41 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN), 42 #endif 43 0, 44 }; 45 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 46 47 /* 48 * All the power management helpers in this file assume at least cluster power 49 * level is supported. 50 */ 51 CASSERT(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL1, 52 assert_max_pwr_lvl_supported_mismatch); 53 54 /* 55 * Ensure that the PLAT_MAX_PWR_LVL is not greater than CSS_SYSTEM_PWR_DMN_LVL 56 * assumed by the CSS layer. 57 */ 58 CASSERT(PLAT_MAX_PWR_LVL <= CSS_SYSTEM_PWR_DMN_LVL, 59 assert_max_pwr_lvl_higher_than_css_sys_lvl); 60 61 /******************************************************************************* 62 * Handler called when a power domain is about to be turned on. The 63 * level and mpidr determine the affinity instance. 64 ******************************************************************************/ 65 int css_pwr_domain_on(u_register_t mpidr) 66 { 67 css_scp_on(mpidr); 68 69 return PSCI_E_SUCCESS; 70 } 71 72 static void css_pwr_domain_on_finisher_common( 73 const psci_power_state_t *target_state) 74 { 75 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 76 77 /* 78 * Perform the common cluster specific operations i.e enable coherency 79 * if this cluster was off. 80 */ 81 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) 82 plat_arm_interconnect_enter_coherency(); 83 } 84 85 /******************************************************************************* 86 * Handler called when a power level has just been powered on after 87 * being turned off earlier. The target_state encodes the low power state that 88 * each level has woken up from. This handler would never be invoked with 89 * the system power domain uninitialized as either the primary would have taken 90 * care of it as part of cold boot or the first core awakened from system 91 * suspend would have already initialized it. 92 ******************************************************************************/ 93 void css_pwr_domain_on_finish(const psci_power_state_t *target_state) 94 { 95 /* Assert that the system power domain need not be initialized */ 96 assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN); 97 98 css_pwr_domain_on_finisher_common(target_state); 99 } 100 101 /******************************************************************************* 102 * Handler called when a power domain has just been powered on and the cpu 103 * and its cluster are fully participating in coherent transaction on the 104 * interconnect. Data cache must be enabled for CPU at this point. 105 ******************************************************************************/ 106 void css_pwr_domain_on_finish_late(const psci_power_state_t *target_state) 107 { 108 /* Program the gic per-cpu distributor or re-distributor interface */ 109 plat_arm_gic_pcpu_init(); 110 111 /* Enable the gic cpu interface */ 112 plat_arm_gic_cpuif_enable(); 113 } 114 115 /******************************************************************************* 116 * Common function called while turning a cpu off or suspending it. It is called 117 * from css_off() or css_suspend() when these functions in turn are called for 118 * power domain at the highest power level which will be powered down. It 119 * performs the actions common to the OFF and SUSPEND calls. 120 ******************************************************************************/ 121 static void css_power_down_common(const psci_power_state_t *target_state) 122 { 123 /* Prevent interrupts from spuriously waking up this cpu */ 124 plat_arm_gic_cpuif_disable(); 125 126 /* Cluster is to be turned off, so disable coherency */ 127 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) { 128 plat_arm_interconnect_exit_coherency(); 129 130 #if HW_ASSISTED_COHERENCY 131 uint32_t reg; 132 133 /* 134 * If we have determined this core to be the last man standing and we 135 * intend to power down the cluster proactively, we provide a hint to 136 * the power controller that cluster power is not required when all 137 * cores are powered down. 138 * Note that this is only an advisory to power controller and is supported 139 * by SoCs with DynamIQ Shared Units only. 140 */ 141 reg = read_clusterpwrdn(); 142 143 /* Clear and set bit 0 : Cluster power not required */ 144 reg &= ~DSU_CLUSTER_PWR_MASK; 145 reg |= DSU_CLUSTER_PWR_OFF; 146 write_clusterpwrdn(reg); 147 #endif 148 } 149 } 150 151 /******************************************************************************* 152 * Handler called when a power domain is about to be turned off. The 153 * target_state encodes the power state that each level should transition to. 154 ******************************************************************************/ 155 void css_pwr_domain_off(const psci_power_state_t *target_state) 156 { 157 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 158 css_power_down_common(target_state); 159 css_scp_off(target_state); 160 } 161 162 /******************************************************************************* 163 * Handler called when a power domain is about to be suspended. The 164 * target_state encodes the power state that each level should transition to. 165 ******************************************************************************/ 166 void css_pwr_domain_suspend(const psci_power_state_t *target_state) 167 { 168 /* 169 * CSS currently supports retention only at cpu level. Just return 170 * as nothing is to be done for retention. 171 */ 172 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET) 173 return; 174 175 176 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 177 css_power_down_common(target_state); 178 179 /* Perform system domain state saving if issuing system suspend */ 180 if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) { 181 arm_system_pwr_domain_save(); 182 183 /* Power off the Redistributor after having saved its context */ 184 plat_arm_gic_redistif_off(); 185 } 186 187 css_scp_suspend(target_state); 188 } 189 190 /******************************************************************************* 191 * Handler called when a power domain has just been powered on after 192 * having been suspended earlier. The target_state encodes the low power state 193 * that each level has woken up from. 194 * TODO: At the moment we reuse the on finisher and reinitialize the secure 195 * context. Need to implement a separate suspend finisher. 196 ******************************************************************************/ 197 void css_pwr_domain_suspend_finish( 198 const psci_power_state_t *target_state) 199 { 200 /* Return as nothing is to be done on waking up from retention. */ 201 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET) 202 return; 203 204 /* Perform system domain restore if woken up from system suspend */ 205 if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) 206 /* 207 * At this point, the Distributor must be powered on to be ready 208 * to have its state restored. The Redistributor will be powered 209 * on as part of gicv3_rdistif_init_restore. 210 */ 211 arm_system_pwr_domain_resume(); 212 213 css_pwr_domain_on_finisher_common(target_state); 214 215 /* Enable the gic cpu interface */ 216 plat_arm_gic_cpuif_enable(); 217 } 218 219 /******************************************************************************* 220 * Handlers to shutdown/reboot the system 221 ******************************************************************************/ 222 void __dead2 css_system_off(void) 223 { 224 css_scp_sys_shutdown(); 225 } 226 227 void __dead2 css_system_reset(void) 228 { 229 css_scp_sys_reboot(); 230 } 231 232 /******************************************************************************* 233 * Handler called when the CPU power domain is about to enter standby. 234 ******************************************************************************/ 235 void css_cpu_standby(plat_local_state_t cpu_state) 236 { 237 unsigned int scr; 238 239 assert(cpu_state == ARM_LOCAL_STATE_RET); 240 241 scr = read_scr_el3(); 242 /* 243 * Enable the Non secure interrupt to wake the CPU. 244 * In GICv3 affinity routing mode, the non secure group1 interrupts use 245 * the PhysicalFIQ at EL3 whereas in GICv2, it uses the PhysicalIRQ. 246 * Enabling both the bits works for both GICv2 mode and GICv3 affinity 247 * routing mode. 248 */ 249 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); 250 isb(); 251 dsb(); 252 wfi(); 253 254 /* 255 * Restore SCR to the original value, synchronisation of scr_el3 is 256 * done by eret while el3_exit to save some execution cycles. 257 */ 258 write_scr_el3(scr); 259 } 260 261 /******************************************************************************* 262 * Handler called to return the 'req_state' for system suspend. 263 ******************************************************************************/ 264 void css_get_sys_suspend_power_state(psci_power_state_t *req_state) 265 { 266 unsigned int i; 267 268 /* 269 * System Suspend is supported only if the system power domain node 270 * is implemented. 271 */ 272 assert(PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL); 273 274 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) 275 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; 276 } 277 278 /******************************************************************************* 279 * Handler to query CPU/cluster power states from SCP 280 ******************************************************************************/ 281 int css_node_hw_state(u_register_t mpidr, unsigned int power_level) 282 { 283 return css_scp_get_power_state(mpidr, power_level); 284 } 285 286 /* 287 * The system power domain suspend is only supported only via 288 * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain 289 * will be downgraded to the lower level. 290 */ 291 static int css_validate_power_state(unsigned int power_state, 292 psci_power_state_t *req_state) 293 { 294 int rc; 295 rc = arm_validate_power_state(power_state, req_state); 296 297 /* 298 * Ensure that we don't overrun the pwr_domain_state array in the case 299 * where the platform supported max power level is less than the system 300 * power level 301 */ 302 303 #if (PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL) 304 305 /* 306 * Ensure that the system power domain level is never suspended 307 * via PSCI CPU SUSPEND API. Currently system suspend is only 308 * supported via PSCI SYSTEM SUSPEND API. 309 */ 310 311 req_state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] = 312 ARM_LOCAL_STATE_RUN; 313 #endif 314 315 return rc; 316 } 317 318 /* 319 * Custom `translate_power_state_by_mpidr` handler for CSS. Unlike in the 320 * `css_validate_power_state`, we do not downgrade the system power 321 * domain level request in `power_state` as it will be used to query the 322 * PSCI_STAT_COUNT/RESIDENCY at the system power domain level. 323 */ 324 static int css_translate_power_state_by_mpidr(u_register_t mpidr, 325 unsigned int power_state, 326 psci_power_state_t *output_state) 327 { 328 return arm_validate_power_state(power_state, output_state); 329 } 330 331 /******************************************************************************* 332 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard 333 * platform will take care of registering the handlers with PSCI. 334 ******************************************************************************/ 335 plat_psci_ops_t plat_arm_psci_pm_ops = { 336 .pwr_domain_on = css_pwr_domain_on, 337 .pwr_domain_on_finish = css_pwr_domain_on_finish, 338 .pwr_domain_on_finish_late = css_pwr_domain_on_finish_late, 339 .pwr_domain_off = css_pwr_domain_off, 340 .cpu_standby = css_cpu_standby, 341 .pwr_domain_suspend = css_pwr_domain_suspend, 342 .pwr_domain_suspend_finish = css_pwr_domain_suspend_finish, 343 .system_off = css_system_off, 344 .system_reset = css_system_reset, 345 .validate_power_state = css_validate_power_state, 346 .validate_ns_entrypoint = arm_validate_psci_entrypoint, 347 .translate_power_state_by_mpidr = css_translate_power_state_by_mpidr, 348 .get_node_hw_state = css_node_hw_state, 349 .get_sys_suspend_power_state = css_get_sys_suspend_power_state, 350 351 #if defined(PLAT_ARM_MEM_PROT_ADDR) 352 .mem_protect_chk = arm_psci_mem_protect_chk, 353 .read_mem_protect = arm_psci_read_mem_protect, 354 .write_mem_protect = arm_nor_psci_write_mem_protect, 355 #endif 356 #if CSS_USE_SCMI_SDS_DRIVER 357 .system_reset2 = css_system_reset2, 358 #endif 359 }; 360