| 6ef63af6 | 14-Dec-2022 |
Raef Coles <raef.coles@arm.com> |
feat(rss): add TC platform UUIDs for RSS images
Add platform fiptool and UUIDs to the TC platform, to allow RSS images
to be inserted into and used from FIPs
Change-Id: Ic8e11bd4a766bdc616af7dee60d
feat(rss): add TC platform UUIDs for RSS images
Add platform fiptool and UUIDs to the TC platform, to allow RSS images
to be inserted into and used from FIPs
Change-Id: Ic8e11bd4a766bdc616af7dee60d44fc5d1f6e7b6
Signed-off-by: Raef Coles <raef.coles@arm.com>
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| 36ec4c75 | 09-Jan-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "fix(plat/tc): increase TC_TZC_DRAM1_SIZE" into integration |
| 7e3f6a87 | 11-Apr-2022 |
Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
fix(plat/tc): increase TC_TZC_DRAM1_SIZE
Increase TC_TZC_DRAM1_SIZE for Trusty image and its memory size.
Update OP-TEE reserved memory range in DTS
Change-Id: Iad433c3c155f28860b15bde2398df6534871
fix(plat/tc): increase TC_TZC_DRAM1_SIZE
Increase TC_TZC_DRAM1_SIZE for Trusty image and its memory size.
Update OP-TEE reserved memory range in DTS
Change-Id: Iad433c3c155f28860b15bde2398df653487189dd
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
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| 1ae75529 | 21-Nov-2022 |
Andre Przywara <andre.przywara@arm.com> |
feat(fvp): emulate trapped RNDR
When a platform decides to use FEAT_RNG_TRAP, every RNDR or RNDRSS read
will trap into EL3. The platform can then emulate those instructions, by
either executing the
feat(fvp): emulate trapped RNDR
When a platform decides to use FEAT_RNG_TRAP, every RNDR or RNDRSS read
will trap into EL3. The platform can then emulate those instructions, by
either executing the real CPU instructions, potentially conditioning the
results, or use rate-limiting or filtering to protect the hardware
entropy pool. Another possiblitiy would be to use some platform specific
TRNG device to get entropy and returning this.
To demonstrate platform specific usage, add a demo implementation for the
FVP: It will execute the actual CPU instruction and just return the
result. This should serve as reference code to implement platform specific
policies.
We change the definition of read_rndr() and read_rndrrs() to use the
alternative sysreg encoding, so that all assemblers can handle that.
Add documentation about the new platform specific RNG handler function.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ibce817b3b06ad20129d15531b81402e3cc3e9a9e
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|
| 15a6c959 | 20-Dec-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "feat(tc): add delegated attest and measurement tests" into integration |
| 95302e4b | 13-Dec-2022 |
laurenw-arm <lauren.wehrmeister@arm.com> |
fix(arm): arm_rotpk_header undefined reference
Moving ARM_ROTPK_S to default to arm_dev_rotpk.S as it was not being
set for Juno cryptocell and this should be the value in most cases.
Change-Id: I5
fix(arm): arm_rotpk_header undefined reference
Moving ARM_ROTPK_S to default to arm_dev_rotpk.S as it was not being
set for Juno cryptocell and this should be the value in most cases.
Change-Id: I56a5a4e61f1ca728b87322b0b09a0d73ed1d5ee0
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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|
| 25dd2172 | 21-Oct-2022 |
Mate Toth-Pal <mate.toth-pal@arm.com> |
feat(tc): add delegated attest and measurement tests
This patch adds Delegated Attestation and Measured Boot tests to the
plat/arm/board/tc platform.
The test suite can be activated by adding the bu
feat(tc): add delegated attest and measurement tests
This patch adds Delegated Attestation and Measured Boot tests to the
plat/arm/board/tc platform.
The test suite can be activated by adding the build time option
`PLATFORM_TEST=1` to the make command. In this case the boot sequence is
not finished, plat_error_handler is called after the tests are run
(regardless of the test result.)
The actual test code is coming from the Trusted-Firmware-M project. Some
of the files of the tf-m-tests and tf-m-extras repo are linked to the
BL31 image.
Versions used for testing:
https://git.trustedfirmware.org/TF-M/tf-m-tests
614e8c358377e4146e8ee13d1246e59d01b4bf1b
https: //git.trustedfirmware.org/TF-M/tf-m-extras
3be9fdd557e6df449de93c2101973fb011699b3d
Change-Id: I98f0f5f760a39d2d7e0dd11d33663ddb75f0b6fc
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
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|
| abd6d7ea | 12-Dec-2022 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "full_dev_rsa_key" into integration
* changes:
docs(arm): add ARM_ROTPK_LOCATION variant full key
feat(arm): add ARM_ROTPK_LOCATION variant full key |
| 5f899286 | 28-Oct-2022 |
laurenw-arm <lauren.wehrmeister@arm.com> |
feat(arm): add ARM_ROTPK_LOCATION variant full key
Add support for ARM_ROTPK_LOCATION=devel_full_dev_rsa_key, which
implements the scenario where the platform provides the full ROTPK, as
opposed to
feat(arm): add ARM_ROTPK_LOCATION variant full key
Add support for ARM_ROTPK_LOCATION=devel_full_dev_rsa_key, which
implements the scenario where the platform provides the full ROTPK, as
opposed to the hash of it. This returns a 2kB development RSA key
embedded into the firmware.
The motivation for this patch is to extend our test coverage in the CI.
Right now, the authentication framework allows platforms to return
either the full ROTPK or a hash of it (*). However, the FVP platform
only supports returning a hash currently so we cannot easily exercise
the full key scenario. This patch adds that capability.
(*) Or even no key at all if it's not deployed on the platform yet, as
is typically the case on pre-production/developement platforms.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ie869cca1082410e63894e2b7dea2d31155684105
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|
| 557bc9dc | 09-Dec-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "tonnad01/gcc_warn_fix" into integration
* changes:
fix(scmi): change function prototype to fix gcc error
fix(rdn1edge): change variable type to fix gcc sign conversion
Merge changes from topic "tonnad01/gcc_warn_fix" into integration
* changes:
fix(scmi): change function prototype to fix gcc error
fix(rdn1edge): change variable type to fix gcc sign conversion error
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|
| a0f256b0 | 08-Dec-2022 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "fix(rmmd): add missing padding to RMM Boot Manifest and initialize it" into integration |
| f0f2c903 | 07-Dec-2022 |
Tony K Nadackal <tony.nadackal@arm.com> |
fix(scmi): change function prototype to fix gcc error
Change function prototype of plat_css_get_scmi_info() to fix the GCC
sign conversion error "comparison between signed and unsigned integer
expre
fix(scmi): change function prototype to fix gcc error
Change function prototype of plat_css_get_scmi_info() to fix the GCC
sign conversion error "comparison between signed and unsigned integer
expressions". Changing channel_id type to unsigned int since it can
never be a negative value.
Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Change-Id: I579b21497329db40897c10d86c8fc68e4877f3db
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|
| 3a3e0e53 | 07-Dec-2022 |
Tony K Nadackal <tony.nadackal@arm.com> |
fix(rdn1edge): change variable type to fix gcc sign conversion error
Change variable type in function bl31_platform_setup() to fix the GCC
sign conversion error "comparison between signed and unsign
fix(rdn1edge): change variable type to fix gcc sign conversion error
Change variable type in function bl31_platform_setup() to fix the GCC
sign conversion error "comparison between signed and unsigned integer
expressions".
Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Change-Id: Iff914bd7ad521883723c8fb34dd893412cce7fc5
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|
| dc0ca64e | 01-Dec-2022 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
fix(rmmd): add missing padding to RMM Boot Manifest and initialize it
This patch also:
* Enforces the check of RES0 fields on EL3-RMM boot interface
and manifest
* Fixes a couple of
fix(rmmd): add missing padding to RMM Boot Manifest and initialize it
This patch also:
* Enforces the check of RES0 fields on EL3-RMM boot interface
and manifest
* Fixes a couple of nits on the EL3-RMM Boot Interface
documentation.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Idb9e38f9fcda2ba0655646a1e2c4fdbabd5cdc40
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|
| 0312769f | 06-Dec-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "refactor(arm): remove unused global" into integration |
| d8359cfa | 04-Dec-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(arm): remove unused global
Removed unused global from the assembly file.
Change-Id: I17ab70aa888af27865a9fb4436495197f460780f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> |
| 7f3d9eae | 18-Nov-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(fvp): pass platform metadata as a function's argument
Based on the prototype modification of the event_log_measure_and_record
function in the previous patch, platform metadata was passed as
refactor(fvp): pass platform metadata as a function's argument
Based on the prototype modification of the event_log_measure_and_record
function in the previous patch, platform metadata was passed as an
argument.
Change-Id: Id1bf59c243c483d7e32152f094c693e95d29fe2b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| 42c70c08 | 11-Nov-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
build: deprecate Arm TC0 FVP platform
Arm has decided to deprecate the TC0 platform. The development of
software and fast models for TC0 platform has been discontinued.
TC0 platform has been superse
build: deprecate Arm TC0 FVP platform
Arm has decided to deprecate the TC0 platform. The development of
software and fast models for TC0 platform has been discontinued.
TC0 platform has been superseded by the TC1 and TC2 platforms,
which are already supported in TF-A and CI repositories.
Change-Id: I0269816a6ee733f732669027eae4e14cd60b6084
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| f41e23ea | 10-Nov-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "mp/ras_refactoring" into integration
* changes:
docs: document do_panic() and panic() helper functions
fix(ras): restrict RAS support for NS world |
| 5605c442 | 09-Nov-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "rdn2cfg2_spi_support" into integration
* changes:
feat(rdn2): enable extended SPI support
feat(rdn2): add SPI ID ranges for RD-N2 multichip platform |
| 46cc41d5 | 10-Oct-2022 |
Manish Pandey <manish.pandey2@arm.com> |
fix(ras): restrict RAS support for NS world
Current RAS framework in TF-A only supports handling errors originating
from NS world but the HANDLE_EA_EL3_FIRST flag configures it for all
lower Els. To
fix(ras): restrict RAS support for NS world
Current RAS framework in TF-A only supports handling errors originating
from NS world but the HANDLE_EA_EL3_FIRST flag configures it for all
lower Els. To make the current design of RAS explicit, rename this macro
to HANDLE_EA_EL3_FIRST_NS and set EA bit in scr_el3 only when
switching to NS world.
Note: I am unaware of any platform which traps errors originating in
Secure world to EL3, if there is any such platform then it need to
be explicitly implemented in TF-A
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: If58eb201d8fa792c16325c85c26056e9b409b750
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|
| 07dc8ba9 | 19-Oct-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
build: deprecate Arm rdn1edge and sgi575 FVP platforms
Arm has decided to deprecate the sgi575 and rdn1edge platforms.
The development of software and fast models for these platforms
has been discon
build: deprecate Arm rdn1edge and sgi575 FVP platforms
Arm has decided to deprecate the sgi575 and rdn1edge platforms.
The development of software and fast models for these platforms
has been discontinued. rdn1edge platform has been superseded by the
rdn2 platform, which is already supported in TF-A and CI work is
underway for this platform.
Change-Id: If2228fb73549b244c3a5b0e5746617b3f24fe771
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| 108488f9 | 14-Sep-2022 |
Vivek Gautam <vivek.gautam@arm.com> |
feat(rdn2): enable extended SPI support
Enable the GIC_EXT_INTID configuration to support extended interrupt
IDs for RD-N2 multichip platform.
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Cha
feat(rdn2): enable extended SPI support
Enable the GIC_EXT_INTID configuration to support extended interrupt
IDs for RD-N2 multichip platform.
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ic8d59ba0e692e5f13f3cdeffc64d76cd4741aa11
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|
| 9f0835e9 | 12-Jul-2022 |
Vivek Gautam <vivek.gautam@arm.com> |
feat(rdn2): add SPI ID ranges for RD-N2 multichip platform
Add the SPI ID ranges for various chips on RD-N2 multichip platform
(rdn2cfg2). Also fix the max SPI ID for chip#0 that was incorrectly
set
feat(rdn2): add SPI ID ranges for RD-N2 multichip platform
Add the SPI ID ranges for various chips on RD-N2 multichip platform
(rdn2cfg2). Also fix the max SPI ID for chip#0 that was incorrectly
set.
The SPI ranges for rdn2cfg2 platform are as shown below:
============================================
Chip# | CHIP_START_INTID | CHIP_END_INTID
============================================
0 | 32 | 511
1 | 512 | 991
2 | 4096 | 4575
3 | 4576 | 5055
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: I146944af1ffe52c300eef2ef48b1077a9559bf41
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| 0271eddb | 12-Oct-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
feat(fvp): build delegated attestation in BL31
Right now, the delegated attestation module is not used in TF-A. This
means it's not even getting built and so the CI system cannot detect
build regres
feat(fvp): build delegated attestation in BL31
Right now, the delegated attestation module is not used in TF-A. This
means it's not even getting built and so the CI system cannot detect
build regressions.
Eventually, delegated attestation will be involved in a new runtime
service exposed by BL31 to lower exception levels. We are not there
yet but let's already include it into BL31 image, so we get build
coverage and static analysis on the code. Note that we make sure to
cover both PLAT_RSS_NOT_SUPPORTED=0 and PLAT_RSS_NOT_SUPPORTED=1
configurations.
Delegated attestation is currently made dependent on measured boot
support. This dependency is not at the source code level (attestation
code does not invoke any measured boot interfaces) but it is rather a
logical dependency: attestation without boot measurements is not very
useful...
For now, this is good enough for our purpose but the conditions under
which the attestation code is included might change in the future.
Change-Id: I616715c3dd0418a1bbf1019df3ff9acd8461e705
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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