feat(rdfremont): initialize GPT on GPC SMMU block

GPC SMMU does granule protection checks (GPC) for accesses originating
from the system control block and GIC on RD-Fremont platforms. The GPC
check

feat(rdfremont): initialize GPT on GPC SMMU block

GPC SMMU does granule protection checks (GPC) for accesses originating
from the system control block and GIC on RD-Fremont platforms. The GPC
check on this is disabled by the boot firmware. Configure the GPC SMMU
to enable GPC.

The transactions on GPC SMMU should be allowed during boot stages so
don't perform smmuv3_security_init() for this SMMU instance.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: I3400c57fe264582a45c6a26f9dae8c669e8a8047

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feat(rdfremont): update Root registers page offset for SMMUv3

SMMUv3 with RME on RD-Fremont platform variants supports Root and Realm
register pages. The page offset for Root and Realm register page

feat(rdfremont): update Root registers page offset for SMMUv3

SMMUv3 with RME on RD-Fremont platform variants supports Root and Realm
register pages. The page offset for Root and Realm register pages is a
platform configurable option. Update the Root registers page offset for
RD-Fremont platform variants.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ib3df7d7b9e54219d49b4d77a1fc5846096f1c78c

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feat(rdfremont): enable MTE2 if present on the platform

MTE2 is an optional feature that could be part of platforms based on Arm
V8.5 or above. If this feature is implemented on the platform, lower

feat(rdfremont): enable MTE2 if present on the platform

MTE2 is an optional feature that could be part of platforms based on Arm
V8.5 or above. If this feature is implemented on the platform, lower ELs
could potentially access the feature registers leading to EL3 traps.
Therefore, set MTE2 build option to '2' to enable the feature only if
its implemented on the platform.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Idc04b7f3851a2481e4c6bea426a3f09be145b899

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feat(rdfremont): enable SVE for SWD and NS

Enable SVE support for non secure and secure worlds for RD-Fremont
variants.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Signed-off-by: Rohit Mathe

feat(rdfremont): enable SVE for SWD and NS

Enable SVE support for non secure and secure worlds for RD-Fremont
variants.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Idcb309d031a1e10740dd365bb65570f8d2ce3a05

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feat(rdfremont): enable AMU if present on the platform

Set build-option ENABLE_FEAT_AMU to 2 so that AMU is enabled if the
feature is implemented on the platform. This would ensure that lower ELs
co

feat(rdfremont): enable AMU if present on the platform

Set build-option ENABLE_FEAT_AMU to 2 so that AMU is enabled if the
feature is implemented on the platform. This would ensure that lower ELs
could access system registers relevant to AMU registers without causing
a trap to EL3.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I567ac9b0d76b613593d37ea45b4955b423ff5e6c

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feat(rdfremont): enable MPAM if present on the platform

Set build-option ENABLE_FEAT_MPAM to 2 so that access to MPAM related
registers from lower ELs don't trap to EL3.

Signed-off-by: Rohit Mathew

feat(rdfremont): enable MPAM if present on the platform

Set build-option ENABLE_FEAT_MPAM to 2 so that access to MPAM related
registers from lower ELs don't trap to EL3.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I4c5753c415461e5ffc79e371ae00cc6e6dd087f9

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feat(rdfremont): add DRAM pas entries in pas table for multichip

RD-Fremont-Cfg2 supports 8 DRAM banks compared to RD-Fremont and
RD-Fremont-Cfg1, which only support 2. So add PAS entries for
all th

feat(rdfremont): add DRAM pas entries in pas table for multichip

RD-Fremont-Cfg2 supports 8 DRAM banks compared to RD-Fremont and
RD-Fremont-Cfg1, which only support 2. So add PAS entries for
all the DRAM banks in the PAS table for RD-Fremont-Cfg2, ensuring proper
access controls to these regions.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ib09b44569ea088f35529a1c983d3db727d86e262

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feat(rdfremont): add implementation for GPT setup

Since GPT setup has been delegated to the platform, add an
implementation for plat_bl2_gpt_setup in accordance with the
specification for RD-Fremont

feat(rdfremont): add implementation for GPT setup

Since GPT setup has been delegated to the platform, add an
implementation for plat_bl2_gpt_setup in accordance with the
specification for RD-Fremont variants.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I1ff47249ce304f1c188850282d92c64cae463383

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feat(rdfremont): integrate DTS files for RD-Fremont variants

This update incorporates essential device tree (DTS) files for
RD-Fremont variants. The inclusion covers DTS for platform and config
ID,

feat(rdfremont): integrate DTS files for RD-Fremont variants

This update incorporates essential device tree (DTS) files for
RD-Fremont variants. The inclusion covers DTS for platform and config
ID, NT_FW_CONFIG, and TB_FW_CONFIG, enhancing device tree support for
RD-Fremont within the project.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ibf898f963d971fe9b07cfa518244c47a8aced81e

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feat(rdfremont): add support for RD-Fremont-Cfg2

Add board support for RD-Fremont-Cfg2 platform, which is a quad chip
variant of RD-Fremont. Each chip has reduced core count of four CPUs as
compared

feat(rdfremont): add support for RD-Fremont-Cfg2

Add board support for RD-Fremont-Cfg2 platform, which is a quad chip
variant of RD-Fremont. Each chip has reduced core count of four CPUs as
compared to single chip RD-Fremont platform.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I9b79f0eef210afecaa15e381414479027617e44a

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feat(rdfremont): add support for RD-Fremont-Cfg1

Add the required source and header files to support RD-Fremont-Cfg1,
which is a variant of RD-Fremont. RD-Fremont-Cfg1 hosts a smaller mesh
and lower

feat(rdfremont): add support for RD-Fremont-Cfg1

Add the required source and header files to support RD-Fremont-Cfg1,
which is a variant of RD-Fremont. RD-Fremont-Cfg1 hosts a smaller mesh
and lower number of cores when compared with RD-Fremont.

Signed-off-by: Shriram K <shriram.k@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I720b0e76174123c8aab64b39e9468b28614607b9

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feat(rdfremont): add support for RD-Fremont

Add the required source and header files to support RD-Fremont.
Additionally, create a makefile for building the platform.

Co-developed-by: Harry Moulton

feat(rdfremont): add support for RD-Fremont

Add the required source and header files to support RD-Fremont.
Additionally, create a makefile for building the platform.

Co-developed-by: Harry Moulton <harry.moulton@arm.com>
Signed-off-by: Harry Moulton <harry.moulton@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I03b6913b08d488c86a5f4638ef6cd8b0f5c43a9a

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feat(neoverse-rd): add multichip pas entries

RD-Fremont-Cfg2, the quad-chip variant of RD-Fremont supports 8 DRAM
banks compared to RD-Fremont and RD-Fremont-Cfg1, which only support 2.
Therefore, d

feat(neoverse-rd): add multichip pas entries

RD-Fremont-Cfg2, the quad-chip variant of RD-Fremont supports 8 DRAM
banks compared to RD-Fremont and RD-Fremont-Cfg1, which only support 2.
Therefore, define PAS entry mappings for all the DRAM banks, so that
they could be utilized on the multichip variant.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Ief235581c0066a95528235b9821646f864e14d3a

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feat(neoverse-rd): add pas definitions for third gen platforms

Since the GPT setup is now delegated to the platform, each platform
needs to include PAS definitions according to its specifications. T

feat(neoverse-rd): add pas definitions for third gen platforms

Since the GPT setup is now delegated to the platform, each platform
needs to include PAS definitions according to its specifications. This
commit adds PAS definitions specifically tailored for RD-Fremont
variants.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I1a23029a74401fb1faa70bb6c2e66093ed08c45a

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feat(neoverse-rd): add DRAM layout for third gen platforms

Given the differences in memory map of the third generation reference
design platforms, it is necessary to move away from the common DRAM
l

feat(neoverse-rd): add DRAM layout for third gen platforms

Given the differences in memory map of the third generation reference
design platforms, it is necessary to move away from the common DRAM
layout present as part of arm_def.h. Therefore, introduce definitions
and necessary carveouts within DRAM to define a new DRAM layout for
these platforms.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I79af066f41259f147febdc3c00447db5be995799

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feat(neoverse-rd): add SRAM layout for third gen platforms

Given the differences in memory map and additional RME requirements for
the V3 CPU based platforms, it is necessary to move away from the c

feat(neoverse-rd): add SRAM layout for third gen platforms

Given the differences in memory map and additional RME requirements for
the V3 CPU based platforms, it is necessary to move away from the common
SRAM layout present as part of arm_def.h. Therefore, introduce
definitions and necessary carveouts within SRAM to define a new SRAM
layout for these platforms.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I2d0ef65abde66da7523dd9e09036c7803978570c

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feat(neoverse-rd): add firmware definitions for third gen platforms

Add firmware definitions for the third generation of platforms. The
following files are added -

- nrd_css_fw_def3.h: for CSS firm

feat(neoverse-rd): add firmware definitions for third gen platforms

Add firmware definitions for the third generation of platforms. The
following files are added -

- nrd_css_fw_def3.h: for CSS firmware definitions
- nrd_ros_fw_def3.h : for RoS firmware definitions
- nrd_plat_arm_def3.h: for platform port macros

All the common files for these platforms are housed under nrd3
directory.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I085d609cfe1686d28d1c467fb34d45af47e00eb6

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feat(neoverse-rd): add RoS definitions for third gen platforms

Add RoS definitions for third generation of platforms. Common
definitions for such platforms would be housed in the nrd3 directory
unde

feat(neoverse-rd): add RoS definitions for third gen platforms

Add RoS definitions for third generation of platforms. Common
definitions for such platforms would be housed in the nrd3 directory
under includes.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I2062c71676f27b4d17a3069b955565670f62a76c

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feat(neoverse-rd): add CSS definitions for third gen platforms

Add CSS definitions for the third generation of reference design
platforms. Common definitions for such platforms would be housed in th

feat(neoverse-rd): add CSS definitions for third gen platforms

Add CSS definitions for the third generation of reference design
platforms. Common definitions for such platforms would be housed in the
nrd3 directory under includes.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Id271ebdf5dcc1d7b598606c313208ab85662795d

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refactor(neoverse-rd): remove soc_css.mk from common makefile

The soc_css.mk file within the plat/arm/soc module currently implements
initialization functions for the PCIe controller and NIC400 with

refactor(neoverse-rd): remove soc_css.mk from common makefile

The soc_css.mk file within the plat/arm/soc module currently implements
initialization functions for the PCIe controller and NIC400 within the
SOC specification. However, as none of the Neoverse reference design
platforms necessitate the initialization of PCIe or NIC400, remove the
soc_css.mk from the common makefile.

Additionally, empty initialization functions for PCIe and NIC400 are
added to satisfy the requirements of the plat/arm common code, which
expects these functions to be present.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Ia431af62f48fc224962d64902dd3acfbf0b93935

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refactor(neoverse-rd): unify GIC SPI range macros

The existing macros representing GIC SPI minimum and maximum for
multichip platforms lack a consistent naming convention. To address
this, establish

refactor(neoverse-rd): unify GIC SPI range macros

The existing macros representing GIC SPI minimum and maximum for
multichip platforms lack a consistent naming convention. To address
this, establish the convention "NRD_CHIP<x>_SPI_MIN" and
"NRD_CHIP<x>_SPI_MAX" for use across all Neoverse Reference Design
multichip platforms.

Furthermore, extend this naming convention to RD-N2-Cfg2 and introduce
similar macros.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Idca2a8c66579f05e712e3b6e95204fedc122cf23

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refactor(neoverse-rd): clean-up nrd_plat_arm_def2.h file

Consolidate and organize platform port definitions within the
nrd_plat_arm_def2.h file. Remove direct references to addresses with
correspond

refactor(neoverse-rd): clean-up nrd_plat_arm_def2.h file

Consolidate and organize platform port definitions within the
nrd_plat_arm_def2.h file. Remove direct references to addresses with
corresponding RoS or CSS definitions.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ic43cff90d2cf45760b3f808732754cf7c05a814a

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feat(neoverse-rd): disable SPMD_SPM_AT_SEL2 for N2/V2 platforms

SPMD_SPM_AT_SEL2 is enabled by default for platforms. As the platforms
based on N2/V2 CPUs don't use SPMD_SPM_AT_SEL2, set its value t

feat(neoverse-rd): disable SPMD_SPM_AT_SEL2 for N2/V2 platforms

SPMD_SPM_AT_SEL2 is enabled by default for platforms. As the platforms
based on N2/V2 CPUs don't use SPMD_SPM_AT_SEL2, set its value to 0.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ib503c5552e2b8fee928b2392ba40805664d857d7

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feat(rdn2): enable AMU if present on the platform

Set build-option ENABLE_FEAT_AMU to 2 so that AMU is enabled if the
feature is implemented on the platform. This would ensure that lower ELs
could a

feat(rdn2): enable AMU if present on the platform

Set build-option ENABLE_FEAT_AMU to 2 so that AMU is enabled if the
feature is implemented on the platform. This would ensure that lower ELs
could access system registers relevant to AMU without causing a trap to
EL3.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ic9aa435af54eddacdaa49e69f25893ddaa977e3e

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feat(rdn2): enable MTE2 if present on the platform

MTE2 is an optional feature that could be part of platforms based on Arm
V8.5 or above. If this feature is implemented on the platform, lower ELs
c

feat(rdn2): enable MTE2 if present on the platform

MTE2 is an optional feature that could be part of platforms based on Arm
V8.5 or above. If this feature is implemented on the platform, lower ELs
could potentially access the featre registers leading EL3 traps.
Therefore, set MTE2 build option to '2' to enable the feature only if
its implemented on the platform.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I97c341ac38485937eb18ce9bdcffec26c0e5e76d

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