| 3d630fa2 | 06-Feb-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "jc/psci_spe" into integration
* changes:
fix(spe): invoke spe_disable during power domain off/suspend
feat(psci): add psci_do_manage_extensions API
fix(arm_fpga): hal
Merge changes from topic "jc/psci_spe" into integration
* changes:
fix(spe): invoke spe_disable during power domain off/suspend
feat(psci): add psci_do_manage_extensions API
fix(arm_fpga): halve number of PEs per core
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| 777f1f68 | 18-Jul-2023 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
fix(spe): invoke spe_disable during power domain off/suspend
spe_disable function, disables profiling and flushes all the buffers and
hence needs to be called on power-off/suspend path.
It needs to
fix(spe): invoke spe_disable during power domain off/suspend
spe_disable function, disables profiling and flushes all the buffers and
hence needs to be called on power-off/suspend path.
It needs to be invoked as SPE feature writes to memory as part of
regular operation and not disabling before exiting coherency
could potentially cause issues.
Currently, this is handled only for the FVP. Other platforms need
to replicate this behaviour and is covered as part of this patch.
Calling it from generic psci library code, before the platform specific
actions to turn off the CPUs, will make it applicable for all the
platforms which have ported the PSCI library.
Change-Id: I90b24c59480357e2ebfa3dfc356c719ca935c13d
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
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| d07d4d63 | 10-Jan-2024 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
feat(fvp): delegate FFH RAS handling to SP
This setup helps to mimic an end-to-end RAS handling flow inspired
by real world design with a dedicated RAS secure partition managed
by SPMC.
The detaile
feat(fvp): delegate FFH RAS handling to SP
This setup helps to mimic an end-to-end RAS handling flow inspired
by real world design with a dedicated RAS secure partition managed
by SPMC.
The detailed steps are documented as comments in the relevant source
files introduced in this patch.
Change-Id: I97737c66649f6e49840fa0bdf2e0af4fb6b08fc7
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| 28c79e10 | 30-Jan-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "plat_gpt_setup" into integration
* changes:
feat(arm): move GPT setup to common BL source
feat(arm): retrieve GPT related data from platform
refactor(arm): rename L0/
Merge changes from topic "plat_gpt_setup" into integration
* changes:
feat(arm): move GPT setup to common BL source
feat(arm): retrieve GPT related data from platform
refactor(arm): rename L0/L1 GPT base macros
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| 30019d86 | 25-Oct-2023 |
Sona Mathew <sonarebecca.mathew@arm.com> |
feat(cpufeat): add feature detection for FEAT_CSV2_3
This feature provides support to context save the
SCXTNUM_ELx register. FEAT_CSV2_3 implies the implementation
of FEAT_CSV2_2. FEAT_CSV2_3 is sup
feat(cpufeat): add feature detection for FEAT_CSV2_3
This feature provides support to context save the
SCXTNUM_ELx register. FEAT_CSV2_3 implies the implementation
of FEAT_CSV2_2. FEAT_CSV2_3 is supported in AArch64 state only
and is an optional feature in Arm v8.0 implementations.
This patch adds feature detection for v8.9 feature FEAT_CSV2_3,
adds macros for ID_AA64PFR0_EL1.CSV2 bits [59:56] for detecting
FEAT_CSV2_3 and macro for ENABLE_FEAT_CSV2_3.
Change-Id: Ida9f31e832b5f11bd89eebd6cc9f10ddad755c14
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
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| 86e4859a | 20-Dec-2023 |
Rohit Mathew <Rohit.Mathew@arm.com> |
feat(arm): retrieve GPT related data from platform
For RME-enabled platforms, initializing L0 and L1 tables and enabling
GPC checks is necessary. For systems using BL2 to load firmware images,
the G
feat(arm): retrieve GPT related data from platform
For RME-enabled platforms, initializing L0 and L1 tables and enabling
GPC checks is necessary. For systems using BL2 to load firmware images,
the GPT initialization has to be done in BL2 prior to the image load.
The common Arm platform code currently implements this in the
"arm_bl2_plat_gpt_setup" function, relying on the FVP platform's
specifications (PAS definitions, GPCCR_PPS, and GPCCR_PGS).
Different Arm platforms may have distinct PAS definitions, GPCCR_PPS,
GPCCR_PGS, L0/L1 base, and size. To accommodate these variations,
introduce the "plat_arm_get_gpt_info" API. Platforms must implement
this API to provide the necessary data for GPT setup on RME-enabled
platforms. It is essential to note that these additions are relevant to
platforms under the plat/arm hierarchy that will reuse the
"arm_bl2_plat_gpt_setup" function.
As a result of these new additions, migrate data related to the FVP
platform to its source and header files.
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I4f4c8894c1cda0adc1f83e7439eb372e923f6147
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| 4c79b86e | 10-Jan-2024 |
laurenw-arm <lauren.wehrmeister@arm.com> |
feat(fvp): add CCA CoT in DTB support
Adding support for CCA CoT in DTB. This makes it possible for BL2
to retrieve its chain of trust description from a configuration file
in DTB format. With this,
feat(fvp): add CCA CoT in DTB support
Adding support for CCA CoT in DTB. This makes it possible for BL2
to retrieve its chain of trust description from a configuration file
in DTB format. With this, the CoT description may be updated without
rebuilding BL2 image. This feature can be enabled by building BL2
with COT_DESC_IN_DTB=1 and COT=cca. The default behaviour remains to
embed the CoT description into BL2 image.
Change-Id: I5912aad5ae529281a93a76e6b8f4b89d867445fe
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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| e830e4cd | 05-Sep-2023 |
Kathleen Capella <kathleen.capella@arm.com> |
feat(ff-a): update FF-A version to v1.2
Bump the required FF-A version in framework and manifests to v1.2 as
upstream feature development goes.
Signed-off-by: Kathleen Capella <kathleen.capella@arm
feat(ff-a): update FF-A version to v1.2
Bump the required FF-A version in framework and manifests to v1.2 as
upstream feature development goes.
Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I09d936d4aad89965cfd13f58741d647223b63a34
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| dea307fd | 07-Nov-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(fvp): remove RSS usage
Removed RSS usage from the Base AEM FVP platform, as it wasn't
functional on this platform. The Base AEM FVP platform lacks
support for RSS.
Instead, the TC2 platform
refactor(fvp): remove RSS usage
Removed RSS usage from the Base AEM FVP platform, as it wasn't
functional on this platform. The Base AEM FVP platform lacks
support for RSS.
Instead, the TC2 platform with RSS is available for actual RSS
interface implementation and testing.
Change-Id: I8f68157319399ab526f9e851b26dba903db5c2e7
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| f87e54f7 | 10-Oct-2023 |
Manish Pandey <manish.pandey2@arm.com> |
fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT
This patch removes RAS_FFH_SUPPORT macro which is the combination of
ENABLE_FEAT_RAS and HANDLE_EA_EL3_FIRST_NS. Instead introduce an
inter
fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT
This patch removes RAS_FFH_SUPPORT macro which is the combination of
ENABLE_FEAT_RAS and HANDLE_EA_EL3_FIRST_NS. Instead introduce an
internal macro FFH_SUPPORT which gets enabled when platforms wants
to enable lower EL EA handling at EL3. The internal macro FFH_SUPPORT
will be automatically enabled if HANDLE_EA_EL3_FIRST_NS is enabled.
FFH_SUPPORT along with ENABLE_FEAT_RAS will be used in source files
to provide equivalent check which was provided by RAS_FFH_SUPPORT
earlier. In generic code we needed a macro which could abstract both
HANDLE_EA_EL3_FIRST_NS and RAS_FFH_SUPPORT macros that had limitations.
Former was tied up with NS world only while the latter was tied to RAS
feature.
This is to allow Secure/Realm world to have their own FFH macros
in future.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ie5692ccbf462f5dcc3f005a5beea5aa35124ac73
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| 970a4a8d | 10-Oct-2023 |
Manish Pandey <manish.pandey2@arm.com> |
fix(ras): restrict ENABLE_FEAT_RAS to have only two states
As part of migrating RAS extension to feature detection mechanism, the
macro ENABLE_FEAT_RAS was allowed to have dynamic detection (FEAT_ST
fix(ras): restrict ENABLE_FEAT_RAS to have only two states
As part of migrating RAS extension to feature detection mechanism, the
macro ENABLE_FEAT_RAS was allowed to have dynamic detection (FEAT_STATE
2). Considering this feature does impact execution of EL3 and we need
to know at compile time about the presence of this feature. Do not use
dynamic detection part of feature detection mechanism.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I23858f641f81fbd81b6b17504eb4a2cc65c1a752
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| e8d60a31 | 31-Oct-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "hm/mpam" into integration
* changes:
fix(build): convert tabs and ifdef comparisons
fix(build): disable ENABLE_FEAT_MPAM for Aarch32 |
| 6cc94958 | 31-Oct-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "refactor(fvp): do not use RSS platform token and attestation key APIs" into integration |
| a07b4590 | 31-Oct-2023 |
Harrison Mutai <harrison.mutai@arm.com> |
fix(build): disable ENABLE_FEAT_MPAM for Aarch32
Disable FEAT_MPAM support for Aarch32 as it is not supported, following
[1]. ENABLE_FEAT_MPAM is set to 2 by default for Aarch64 in
arch_features.mk,
fix(build): disable ENABLE_FEAT_MPAM for Aarch32
Disable FEAT_MPAM support for Aarch32 as it is not supported, following
[1]. ENABLE_FEAT_MPAM is set to 2 by default for Aarch64 in
arch_features.mk, eliminating the need for duplication in the platform
makefile.
[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/23710
Change-Id: I1c8b6844254e00e6372900f1c87f995f292ae65c
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| fd7e32b8 | 31-Oct-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "hm/post-image" into integration
* changes:
refactor(fvp): move image handling into generic procedure
refactor(bl2): make post image handling platform-specific |
| 11336fb4 | 30-Oct-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "gr/build_refactor" into integration
* changes:
build(refactor): avoid ifdef comparison
refactor(build): avoid using values for comparison
refactor(build): reorder arc
Merge changes from topic "gr/build_refactor" into integration
* changes:
build(refactor): avoid ifdef comparison
refactor(build): avoid using values for comparison
refactor(build): reorder arch features handling
build(n1sdp): add ARM_ARCH_MAJOR.ARM_ARCH_MINOR
refactor(build): reorder platform Makefile evaluation
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| d638029f | 12-Oct-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
refactor(build): avoid using values for comparison
With changes to refactor to use first platform makefiles
then parse arch_features.mk file 'ENABLE_RME' will be initialised
only when we define duri
refactor(build): avoid using values for comparison
With changes to refactor to use first platform makefiles
then parse arch_features.mk file 'ENABLE_RME' will be initialised
only when we define during build or at arch_features.mk thus
making comparison of 'ENABLE_RME' to '0' incorrect.
So keep BRBE disabled when RME is enabled at main makefile level.
Change-Id: I7e3d99eb444678d63585bd5971ada627cfc4fcc9
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| 48b92c60 | 30-Oct-2023 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "mb/psa-crypto-ecdsa" into integration
* changes:
docs: mark PSA_CRYPTO as an experimental feature
feat(fvp): increase BL1 RW area for PSA_CRYPTO implementation
feat(m
Merge changes from topic "mb/psa-crypto-ecdsa" into integration
* changes:
docs: mark PSA_CRYPTO as an experimental feature
feat(fvp): increase BL1 RW area for PSA_CRYPTO implementation
feat(mbedtls-psa): mbedTLS PSA Crypto with ECDSA
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| 568d406c | 29-Sep-2023 |
Harrison Mutai <harrison.mutai@arm.com> |
refactor(fvp): move image handling into generic procedure
Post image handling of the HW_CONFIG is out-of-scope for
`plat_get_next_bl_params`. Move parts of the code responsible for post
processing o
refactor(fvp): move image handling into generic procedure
Post image handling of the HW_CONFIG is out-of-scope for
`plat_get_next_bl_params`. Move parts of the code responsible for post
processing of loaded images into `bl2_plat_handle_post_image_load` for code
reusability and maintainability.
Change-Id: I476b3d306ebcd4529f5e542ba1063e144920bb5f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| ed567207 | 18-Oct-2023 |
Harrison Mutai <harrison.mutai@arm.com> |
refactor(bl2): make post image handling platform-specific
In certain instances a platform may need to make modifications to an
image after it has been loaded by BL2. The existing common
implementati
refactor(bl2): make post image handling platform-specific
In certain instances a platform may need to make modifications to an
image after it has been loaded by BL2. The existing common
implementation is a thin wrapper for a more generic arm post image
handler. To enable platforms to make changes to images when
they're loaded, move this into platform code.
Change-Id: I44025391056adb2d8a8eb4ea5984257b02027181
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| efd812c3 | 27-Oct-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(cpus): add support for Travis CPU" into integration |
| 94c90ac8 | 08-Aug-2023 |
Harrison Mutai <harrison.mutai@arm.com> |
feat(handoff): port BL31-BL33 interface to fw handoff framework
The firmware handoff framework is a light weight mechanism for sharing
information between bootloader stages. Add support for this fra
feat(handoff): port BL31-BL33 interface to fw handoff framework
The firmware handoff framework is a light weight mechanism for sharing
information between bootloader stages. Add support for this framework at
the handoff boundary between runtime firmware BL31 and NS software on FVP.
Change-Id: Ib02e0e4c20a39e32e06da667caf2ce5a28de1e28
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| eb8700a9 | 11-Sep-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(fvp): do not use RSS platform token and attestation key APIs
Since FVP does not support RSS, RSS APIs used to provide the hardcoded
platform token and attestation key. However, that seems t
refactor(fvp): do not use RSS platform token and attestation key APIs
Since FVP does not support RSS, RSS APIs used to provide the hardcoded
platform token and attestation key. However, that seems to be causing
un-necessary mandating of some PSA crypto definitions, that doesn't
seem appropriate.
Hence to retrieve platform token and realm attestation key, these
RSS APIs calls have been replaced with hardcoded information.
Change-Id: I5fd091025e3444a698b9d387763ce20db6b13ae1
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| a0594add | 19-Sep-2023 |
Juan Pablo Conde <juanpablo.conde@arm.com> |
feat(cpus): add support for Travis CPU
Adding basic CPU library code to support Travis CPU
Change-Id: I3c85e9fab409325d213978888a8f6d6949291258
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.
feat(cpus): add support for Travis CPU
Adding basic CPU library code to support Travis CPU
Change-Id: I3c85e9fab409325d213978888a8f6d6949291258
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
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| ce189383 | 02-Oct-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(fvp): increase BL1 RW area for PSA_CRYPTO implementation
When using PSA Crypto API, few algorithms like ECDSA require a
larger BL1 RW area. Hence added an additional BL1 RW page when
PSA_CRYPTO
feat(fvp): increase BL1 RW area for PSA_CRYPTO implementation
When using PSA Crypto API, few algorithms like ECDSA require a
larger BL1 RW area. Hence added an additional BL1 RW page when
PSA_CRYPTO is selected.
Change-Id: Id6994667641a0b1e36b6a356d7c39a125d62ac01
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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