feat(cpus): add support for caddo cpu

Add basic CPU library code to support Caddo CPU

Change-Id: I4b431771ebe6f23eb02f3301ff656cfcd4956f81
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

feat(cpus): add support for veymont cpu

Add basic CPU library code to support Veymont CPU

Change-Id: I44db5650e7c9cf8fcc368c935574f4702c373dae
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

feat(cpufeat): enable FEAT_AIE support

Implement support for FEAT_AIE, which introduces the AMAIR2_ELx and
MAIR2_ELx system registers, extending the memory attributes described
by {A}MAIR_ELx.
Those

feat(cpufeat): enable FEAT_AIE support

Implement support for FEAT_AIE, which introduces the AMAIR2_ELx and
MAIR2_ELx system registers, extending the memory attributes described
by {A}MAIR_ELx.
Those system registers are trapped by the SCR_EL3.AIEn bit, so set the
bit for the non-secure world context to allow OSes to use the feature.

This is controlled by the ENABLE_FEAT_AIE build flag, which follows the
usual semantics of 2 meaning the feature being runtime detected.
Let the default for this flag be 0, but set it to 2 for the FVP.

Change-Id: Iba2011719013a89f9cb3a4317bde18254f45cd25
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes I44f90daa,I0fed6ef4,I018869d3,I9089b3ad,Ibf5b3a80 into integration

* changes:
refactor(fvp): always build RAS files
fix(fvp): give fvp_ras.c better dependencies
fix(cpufeat): add

Merge changes I44f90daa,I0fed6ef4,I018869d3,I9089b3ad,Ibf5b3a80 into integration

* changes:
refactor(fvp): always build RAS files
fix(fvp): give fvp_ras.c better dependencies
fix(cpufeat): add ras files to the build from a common location
fix(cm): do not restore spsr and elr twice on external aborts
fix(cm): do not save SCR_EL3 on external aborts

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refactor(fvp): always build RAS files

Their processing introduces a circular dependency with the
initialization of ENABLE_FEAT_RAS when it's not set on the commandline.
However, building them when E

refactor(fvp): always build RAS files

Their processing introduces a circular dependency with the
initialization of ENABLE_FEAT_RAS when it's not set on the commandline.
However, building them when ENABLE_FEAT_RAS=0 will not produce any side
effects and the code will never be called. So we can always build the
files to remove the circular check.

Change-Id: I44f90daa193c9b2c853f3fd9b54b67ccc7bace83
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(fvp): give fvp_ras.c better dependencies

PLATFORM_TEST_RAS_FFH should default to 0 when unset. It will always be
defined on the commandline so it needs to be checked for truthfulness.
SDEI_SUPPO

fix(fvp): give fvp_ras.c better dependencies

PLATFORM_TEST_RAS_FFH should default to 0 when unset. It will always be
defined on the commandline so it needs to be checked for truthfulness.
SDEI_SUPPORT will also be used so it must be set.

Change-Id: I0fed6ef40eee82a3624de7bc0c85f5662af4ca3a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "feat(cpufeat): enable FEAT_CPA2 for EL3" into integration

feat(cpufeat): enable FEAT_CPA2 for EL3

FEAT_CPA2 enables checked pointer arithmetic, which in the event
of an arithmetic overflow in pointer generation will result in a
non-canonical pointer being

feat(cpufeat): enable FEAT_CPA2 for EL3

FEAT_CPA2 enables checked pointer arithmetic, which in the event
of an arithmetic overflow in pointer generation will result in a
non-canonical pointer being generated and subsequent address fault.

Note that FEAT_CPA is a trivial implementation that exists in
some hardware purely so it can run CPA2-enabled instructions
without crashing but they don't actually have checked arithmetic,
so FEAT_CPA is not explicitly enabled in TF-A.

Change-Id: I6d2ca7a7e4b986bb9e917aa8baf8091a271c168b
Signed-off-by: John Powell <john.powell@arm.com>

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Merge "chore(tc): align core names to Arm Lumex" into integration

chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/docu

chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/documentation/107771/0102/
C1-Ultra TRM: https://developer.arm.com/documentation/108014/0100/
C1-Premium TRM: https://developer.arm.com/documentation/109416/0100/
C1-Nano TRM: https://developer.arm.com/documentation/107753/0001/

[1]:
https://www.arm.com/product-filter?families=c1%20cpus
https://www.arm.com/products/mobile/compute-subsystems/lumex

Signed-off-by: Min Yao Ng <minyao.ng@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Id4b487ef6a6fd1b00b75b09c5d06d81bce50a15d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "rmm-lfa" into integration

* changes:
feat(rmmd): add RMM_RESERVE_MEMORY SMC handler
feat(rmmd): add per-CPU activation token

feat(rmmd): add RMM_RESERVE_MEMORY SMC handler

At the moment any memory required by an R-EL2 manager (RMM) needs to
be known at compile time: that sets the size of the .data and .bss
segments. Some

feat(rmmd): add RMM_RESERVE_MEMORY SMC handler

At the moment any memory required by an R-EL2 manager (RMM) needs to
be known at compile time: that sets the size of the .data and .bss
segments. Some resources depend on the particular machine this will be
running on, the prime example is TF-RMM's granule array, which needs to
know the maximum memory supported beforehand. Other data structures
might depend on the number of CPU cores.

To provide more flexibility, but keep the memory footprint as small as
possible, let's introduce some memory reservation SMC. Any RMM
implementation can ask EL3 for some memory, and would get the physical
address of a usable chunk of memory back. This must happen at RMM boot
time, so before the RMM concluded the boot phase with the
RMM_BOOT_COMPLETE SMC call. Also there is no provision to free memory
again, this would not be needed for the use case of sizing platform
resources, and avoids the complexity of a full-fledged memory allocator.

Add the new RMM_RESERVE_MEMORY command to the implementation defined
RMM-EL3 SMC interface, both in code and documentation. The actual memory
reservation is made a platform implementation, but a simple
implementation is provided, which is used for the FVP platform already:
it will just pick the next matching chunk of memory from the top end of
the RMM carveout. This way the memory reservation will grow down from
the end of the carveout, in a stack-like fashion, until it reaches the
end of the RMM payload, located at the beginning of the carveout. Since
secondary cores might also reserve memory at boot time, there is a
spinlock to protect the simple allocation algorithm.
Other platforms can choose to provide a more sophisticated reservation
algorithm, for instance one taking NUMA locality into account.

This patch just provides the call, at this point there is no obligation
to use the feature, although future TF-RMM versions would rely on it.

Change-Id: I096ac8870ee38f44e18850779fcae829a43a8fd1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes from topic "xl/separate-bl2" into integration

* changes:
feat(fwu): documentation for BL2 separation
feat(fwu): separate bl2 image from rest of the FIP
feat(fwu): create flag for

Merge changes from topic "xl/separate-bl2" into integration

* changes:
feat(fwu): documentation for BL2 separation
feat(fwu): separate bl2 image from rest of the FIP
feat(fwu): create flag for BL2 separation

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Merge "feat(arm): unify Linux kernel as BL33 handling" into integration

feat(arm): unify Linux kernel as BL33 handling

Streamlines and unifies how Arm platforms pass arguments to the Linux
kernel when it is loaded as BL33. It replaces the FVP specific macro
`FVP_HW_CONF

feat(arm): unify Linux kernel as BL33 handling

Streamlines and unifies how Arm platforms pass arguments to the Linux
kernel when it is loaded as BL33. It replaces the FVP specific macro
`FVP_HW_CONFIG_ADDR` with a common macro `ARM_HW_CONFIG_ADDR` for
accessing the device tree blob base address.

For FVP the DT address is set to use `ARM_PRELOADED_DTB_BASE` if
provided, falling back to a default address otherwise.

This provides a consistent mechanism for Arm platforms to define and
override the DTB base address used during kernel handoff. It reduces the
chance of misconfiguration, and simplifies platform integration.

Change-Id: Ib668dbb1de9d42cf41c0b0ee9a316f054891752a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fwu): separate bl2 image from rest of the FIP

Create a separate partition for BL2 image in the GPT.
Modify the makefile to package BL2 image and its certificates
into a different FIP image.

Ch

feat(fwu): separate bl2 image from rest of the FIP

Create a separate partition for BL2 image in the GPT.
Modify the makefile to package BL2 image and its certificates
into a different FIP image.

Change-Id: I950883ea0c393a2a063ad9e51bb963cbac742705
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge "feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support" into integration

Merge "feat(cpus): add support for Canyon CPU" into integration

feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support

Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to

feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support

Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.

When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.

At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e

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feat(cpus): add support for Canyon CPU

Add basic CPU library code to support the Canyon CPU.

Change-Id: I82edc4384c4fe35ec2cf6b4bfd877a24ad8725dc
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
S

feat(cpus): add support for Canyon CPU

Add basic CPU library code to support the Canyon CPU.

Change-Id: I82edc4384c4fe35ec2cf6b4bfd877a24ad8725dc
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Signed-off-by: Min Yao Ng <minyao.ng@arm.com>
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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Merge changes from topic "bk/gicv5_full" into integration

* changes:
feat(fvp): add a GICv5 device tree
refactor(fvp): factor out interrupt information from the dts

feat(fvp): add a GICv5 device tree

Tested with Linux v6.17-rc1, it boots as long as cpu idle is disabled.

Change-Id: Iadeb157e9d911c4228dc62c5610676f4c07f6c11
Co-developed-by: Sascha Bischoff <sasc

feat(fvp): add a GICv5 device tree

Tested with Linux v6.17-rc1, it boots as long as cpu idle is disabled.

Change-Id: Iadeb157e9d911c4228dc62c5610676f4c07f6c11
Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Co-developed-by: Lorenzo Pieralisi <lorenzo.pieralisi2@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "hm/dt" into integration

* changes:
refactor(arm): unify SPSR retrieval logic
feat(fvp): enable kernel dt convention

feat(fvp): enable kernel dt convention

Enable USE_KERNEL_DT_CONVENTION for the FVP platform to pass the DT blob
(DTB) in x0 to BL33. This aligns with the Linux boot protocol as
described in Document

feat(fvp): enable kernel dt convention

Enable USE_KERNEL_DT_CONVENTION for the FVP platform to pass the DT blob
(DTB) in x0 to BL33. This aligns with the Linux boot protocol as
described in Documentation/arm64/booting.rst.

In addition:

- Clean up legacy ARM_LINUX_KERNEL_AS_BL33 handling since
USE_KERNEL_DT_CONVENTION now implies this mode for DT handoff.
- Override args.arg0 for BL33 to point to ARM_PRELOADED_DTB_BASE in
RESET_TO_BL31.
- Skip setting the primary MPID in x0 when using this convention.

Change-Id: Ieea8cfe68104b82038b9311613abf13afe7b48f1
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topics "refactor_stmm", "stmm_crb_area", "stmm_with_xferlist" into integration

* changes:
feat(fvp): organize fvp_stmm_manifest.dts
feat(juno): add pseudo CRB area
feat(fvp)

Merge changes from topics "refactor_stmm", "stmm_crb_area", "stmm_with_xferlist" into integration

* changes:
feat(fvp): organize fvp_stmm_manifest.dts
feat(juno): add pseudo CRB area
feat(fvp): add pseudo CRB area
feat(arm): add pseudo CRB area
feat(juno): increase xtable for pseudo CRB
feat(fvp): increase xtable for pseudo CRB for SPMC_AT_EL3
feat(el3-spmc): deliver TPM event log via hob list
feat(el3-spmc): get sp_manifest via xferlist
feat(fvp): tos_fw_config with transfer list
feat(arm): load tos_fw_cfg using xferlist in SPMC_AT_EL3
feat(fvp): increase secure partition's table mapping count
feat(fvp): increase bl2 mmap tables for handoff

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