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cc41b56f |
| 01-Mar-2024 |
Sona Mathew <sonarebecca.mathew@arm.com> |
fix(cpus): workaround for Cortex-X4 erratum 2701112
Cortex-X4 erratum 2701112 is cat B erratum that applies to revision r0p0 and is fixed in r0p1. This erratum affects system configurations that do
fix(cpus): workaround for Cortex-X4 erratum 2701112
Cortex-X4 erratum 2701112 is cat B erratum that applies to revision r0p0 and is fixed in r0p1. This erratum affects system configurations that do not use an Arm interconnect IP.
The workaround for this erratum is not implemented in EL3. The erratum can be enabled/disabled on a platform level. The flag is used when the errata ABI feature is enabled and can assist the Kernel in the process of mitigation of the erratum.
SDEN Documentation: https://developer.arm.com/documentation/SDEN2432808/latest
Change-Id: I8ede1ee75b0ea1658369a0646d8af91d44a8759b Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
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25f55744 |
| 09-Feb-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "feat(fvp): remove left-over RSS usage" into integration
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a1726fa7 |
| 07-Feb-2024 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(fvp): remove left-over RSS usage
Remove any residual RSS usage in the FVP platform, complementing the changes made in commit dea307fd6cca2dad56867e757804224a8654bc38.
Signed-off-by: Manish V B
feat(fvp): remove left-over RSS usage
Remove any residual RSS usage in the FVP platform, complementing the changes made in commit dea307fd6cca2dad56867e757804224a8654bc38.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I9ced272503456361610ec0c7783d270349233926
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4da4a1a6 |
| 07-Feb-2024 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "od/sme" into integration
* changes: fix(fvp): permit enabling SME for SPD=spmd feat(spmd): pass SMCCCv1.3 SVE hint to lower EL
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| #
0b0fd0b4 |
| 03-May-2023 |
Olivier Deprez <olivier.deprez@arm.com> |
fix(fvp): permit enabling SME for SPD=spmd
Essentially revert [1] to permit specifying SME support along with SPD=spmd on FVP platform.
[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmwar
fix(fvp): permit enabling SME for SPD=spmd
Essentially revert [1] to permit specifying SME support along with SPD=spmd on FVP platform.
[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/20764
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Iab15d5a4c966b9f5b265ccde6711765e242abeaa
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| #
17bef224 |
| 05-Feb-2024 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(fvp): delegate FFH RAS handling to SP" into integration
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| #
d07d4d63 |
| 10-Jan-2024 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
feat(fvp): delegate FFH RAS handling to SP
This setup helps to mimic an end-to-end RAS handling flow inspired by real world design with a dedicated RAS secure partition managed by SPMC.
The detaile
feat(fvp): delegate FFH RAS handling to SP
This setup helps to mimic an end-to-end RAS handling flow inspired by real world design with a dedicated RAS secure partition managed by SPMC.
The detailed steps are documented as comments in the relevant source files introduced in this patch.
Change-Id: I97737c66649f6e49840fa0bdf2e0af4fb6b08fc7 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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7516d93d |
| 29-Jan-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(cpufeat): add feature detection for FEAT_CSV2_3" into integration
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| #
30019d86 |
| 25-Oct-2023 |
Sona Mathew <sonarebecca.mathew@arm.com> |
feat(cpufeat): add feature detection for FEAT_CSV2_3
This feature provides support to context save the SCXTNUM_ELx register. FEAT_CSV2_3 implies the implementation of FEAT_CSV2_2. FEAT_CSV2_3 is sup
feat(cpufeat): add feature detection for FEAT_CSV2_3
This feature provides support to context save the SCXTNUM_ELx register. FEAT_CSV2_3 implies the implementation of FEAT_CSV2_2. FEAT_CSV2_3 is supported in AArch64 state only and is an optional feature in Arm v8.0 implementations.
This patch adds feature detection for v8.9 feature FEAT_CSV2_3, adds macros for ID_AA64PFR0_EL1.CSV2 bits [59:56] for detecting FEAT_CSV2_3 and macro for ENABLE_FEAT_CSV2_3.
Change-Id: Ida9f31e832b5f11bd89eebd6cc9f10ddad755c14 Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
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5fddf53c |
| 23-Nov-2023 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "mb/deprecate-rss-for-fvp" into integration
* changes: refactor(fvp): remove RSS usage refactor(rss)!: remove PLAT_RSS_NOT_SUPPORTED build option
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dea307fd |
| 07-Nov-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(fvp): remove RSS usage
Removed RSS usage from the Base AEM FVP platform, as it wasn't functional on this platform. The Base AEM FVP platform lacks support for RSS. Instead, the TC2 platform
refactor(fvp): remove RSS usage
Removed RSS usage from the Base AEM FVP platform, as it wasn't functional on this platform. The Base AEM FVP platform lacks support for RSS. Instead, the TC2 platform with RSS is available for actual RSS interface implementation and testing.
Change-Id: I8f68157319399ab526f9e851b26dba903db5c2e7 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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6f802c44 |
| 02-Nov-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "mp/exceptions" into integration
* changes: docs(ras): update RAS documentation docs(el3-runtime): update BL31 exception vector handling fix(el3-runtime): restrict low
Merge changes from topic "mp/exceptions" into integration
* changes: docs(ras): update RAS documentation docs(el3-runtime): update BL31 exception vector handling fix(el3-runtime): restrict lower el EA handlers in FFH mode fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT fix(ras): restrict ENABLE_FEAT_RAS to have only two states feat(ras): use FEAT_IESB for error synchronization feat(el3-runtime): modify vector entry paths
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f87e54f7 |
| 10-Oct-2023 |
Manish Pandey <manish.pandey2@arm.com> |
fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT
This patch removes RAS_FFH_SUPPORT macro which is the combination of ENABLE_FEAT_RAS and HANDLE_EA_EL3_FIRST_NS. Instead introduce an inter
fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT
This patch removes RAS_FFH_SUPPORT macro which is the combination of ENABLE_FEAT_RAS and HANDLE_EA_EL3_FIRST_NS. Instead introduce an internal macro FFH_SUPPORT which gets enabled when platforms wants to enable lower EL EA handling at EL3. The internal macro FFH_SUPPORT will be automatically enabled if HANDLE_EA_EL3_FIRST_NS is enabled. FFH_SUPPORT along with ENABLE_FEAT_RAS will be used in source files to provide equivalent check which was provided by RAS_FFH_SUPPORT earlier. In generic code we needed a macro which could abstract both HANDLE_EA_EL3_FIRST_NS and RAS_FFH_SUPPORT macros that had limitations. Former was tied up with NS world only while the latter was tied to RAS feature.
This is to allow Secure/Realm world to have their own FFH macros in future.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ie5692ccbf462f5dcc3f005a5beea5aa35124ac73
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970a4a8d |
| 10-Oct-2023 |
Manish Pandey <manish.pandey2@arm.com> |
fix(ras): restrict ENABLE_FEAT_RAS to have only two states
As part of migrating RAS extension to feature detection mechanism, the macro ENABLE_FEAT_RAS was allowed to have dynamic detection (FEAT_ST
fix(ras): restrict ENABLE_FEAT_RAS to have only two states
As part of migrating RAS extension to feature detection mechanism, the macro ENABLE_FEAT_RAS was allowed to have dynamic detection (FEAT_STATE 2). Considering this feature does impact execution of EL3 and we need to know at compile time about the presence of this feature. Do not use dynamic detection part of feature detection mechanism.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I23858f641f81fbd81b6b17504eb4a2cc65c1a752
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e8d60a31 |
| 31-Oct-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "hm/mpam" into integration
* changes: fix(build): convert tabs and ifdef comparisons fix(build): disable ENABLE_FEAT_MPAM for Aarch32
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6cc94958 |
| 31-Oct-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "refactor(fvp): do not use RSS platform token and attestation key APIs" into integration
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| #
a07b4590 |
| 31-Oct-2023 |
Harrison Mutai <harrison.mutai@arm.com> |
fix(build): disable ENABLE_FEAT_MPAM for Aarch32
Disable FEAT_MPAM support for Aarch32 as it is not supported, following [1]. ENABLE_FEAT_MPAM is set to 2 by default for Aarch64 in arch_features.mk,
fix(build): disable ENABLE_FEAT_MPAM for Aarch32
Disable FEAT_MPAM support for Aarch32 as it is not supported, following [1]. ENABLE_FEAT_MPAM is set to 2 by default for Aarch64 in arch_features.mk, eliminating the need for duplication in the platform makefile.
[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/23710
Change-Id: I1c8b6844254e00e6372900f1c87f995f292ae65c Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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11336fb4 |
| 30-Oct-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "gr/build_refactor" into integration
* changes: build(refactor): avoid ifdef comparison refactor(build): avoid using values for comparison refactor(build): reorder arc
Merge changes from topic "gr/build_refactor" into integration
* changes: build(refactor): avoid ifdef comparison refactor(build): avoid using values for comparison refactor(build): reorder arch features handling build(n1sdp): add ARM_ARCH_MAJOR.ARM_ARCH_MINOR refactor(build): reorder platform Makefile evaluation
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d638029f |
| 12-Oct-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
refactor(build): avoid using values for comparison
With changes to refactor to use first platform makefiles then parse arch_features.mk file 'ENABLE_RME' will be initialised only when we define duri
refactor(build): avoid using values for comparison
With changes to refactor to use first platform makefiles then parse arch_features.mk file 'ENABLE_RME' will be initialised only when we define during build or at arch_features.mk thus making comparison of 'ENABLE_RME' to '0' incorrect.
So keep BRBE disabled when RME is enabled at main makefile level.
Change-Id: I7e3d99eb444678d63585bd5971ada627cfc4fcc9 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| #
efd812c3 |
| 27-Oct-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(cpus): add support for Travis CPU" into integration
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| #
cb70aed4 |
| 27-Oct-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(handoff): port BL31-BL33 interface to fw handoff framework" into integration
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| #
94c90ac8 |
| 08-Aug-2023 |
Harrison Mutai <harrison.mutai@arm.com> |
feat(handoff): port BL31-BL33 interface to fw handoff framework
The firmware handoff framework is a light weight mechanism for sharing information between bootloader stages. Add support for this fra
feat(handoff): port BL31-BL33 interface to fw handoff framework
The firmware handoff framework is a light weight mechanism for sharing information between bootloader stages. Add support for this framework at the handoff boundary between runtime firmware BL31 and NS software on FVP.
Change-Id: Ib02e0e4c20a39e32e06da667caf2ce5a28de1e28 Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| #
eb8700a9 |
| 11-Sep-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(fvp): do not use RSS platform token and attestation key APIs
Since FVP does not support RSS, RSS APIs used to provide the hardcoded platform token and attestation key. However, that seems t
refactor(fvp): do not use RSS platform token and attestation key APIs
Since FVP does not support RSS, RSS APIs used to provide the hardcoded platform token and attestation key. However, that seems to be causing un-necessary mandating of some PSA crypto definitions, that doesn't seem appropriate. Hence to retrieve platform token and realm attestation key, these RSS APIs calls have been replaced with hardcoded information.
Change-Id: I5fd091025e3444a698b9d387763ce20db6b13ae1 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| #
a0594add |
| 19-Sep-2023 |
Juan Pablo Conde <juanpablo.conde@arm.com> |
feat(cpus): add support for Travis CPU
Adding basic CPU library code to support Travis CPU
Change-Id: I3c85e9fab409325d213978888a8f6d6949291258 Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.
feat(cpus): add support for Travis CPU
Adding basic CPU library code to support Travis CPU
Change-Id: I3c85e9fab409325d213978888a8f6d6949291258 Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
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| #
0e1dc0f2 |
| 25-Oct-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(mpam): refine MPAM initialization and enablement process" into integration
|