| 96f40c7b | 11-Nov-2025 |
Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com> |
feat(rdaspen/ras): dump the CPER buffer contents
Print the contents of the buffer to verify the fields set.
Change-Id: Ibb0683c99eed17d40ed5ce410fe19fab7e6bb9e6
Signed-off-by: Sanjana Virupakshagou
feat(rdaspen/ras): dump the CPER buffer contents
Print the contents of the buffer to verify the fields set.
Change-Id: Ibb0683c99eed17d40ed5ce410fe19fab7e6bb9e6
Signed-off-by: Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com>
Signed-off-by: Ahmed Tiba <ahmed.tiba@arm.com>
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| cbad38ff | 07-Nov-2025 |
Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com> |
feat(rdaspen/ras): generate CPER at TF-A EL3
Generate CPER buffer at TF-A EL3, that emits the error data,
when there is a CPU RAS error in the system.
The CPER record consists of:
ESB Header
ESB Da
feat(rdaspen/ras): generate CPER at TF-A EL3
Generate CPER buffer at TF-A EL3, that emits the error data,
when there is a CPU RAS error in the system.
The CPER record consists of:
ESB Header
ESB Data Entry
CPER CPU Error Section
- Arm Processor Error Record
- Arm Processor Error Information
- Arm Processor Context Information
Change-Id: I7e9703a69edec15cbb6f0522333700bb8d7007bf
Signed-off-by: Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com>
Signed-off-by: Ahmed Tiba <ahmed.tiba@arm.com>
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| 0702fe72 | 24-May-2025 |
Ahmed Azeem <ahmed.azeem@arm.com> |
feat(rdaspen): event handler for CPU RAS
This patch introduces assembly helpers for cleaning CPU
RAS, and introduces a way to deassert FAULT IRQ generated
from CE injection.
This also enables all i
feat(rdaspen): event handler for CPU RAS
This patch introduces assembly helpers for cleaning CPU
RAS, and introduces a way to deassert FAULT IRQ generated
from CE injection.
This also enables all inband errors to be handled on AP according
to a CPU RAS event handler:
- Skips spurious entries – returns early when
`ERXSTATUS.{V|CE}` is already clear, disposing of queued phantom
interrupts.
- Clears the error record – rewrites `ERXSTATUS_EL1`, zeros
`ERXMISC0`, `PFG_CTL`, and `PFG_CDN`, then logs the post clear state
for firmware trace.
Inband errors only consist of:
- Corrected Errors
- Deferred Errors
- Change the RAS CPU intr handler logs from VERBOSE to WARN.
Change-Id: I7eb8fecb42095551f51c9d1c5752775f1b577970
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Signed-off-by: Ahmed Tiba <ahmed.tiba@arm.com>
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| c16a3b7c | 28-Mar-2025 |
Amr Mohamed <amr.mohamed@arm.com> |
feat(rdaspen): add support for configurable platform's CPU topology
- Add support for passing build time platform's CPU topology, which
defines the number of clusters and CPUs in the platform.
- A
feat(rdaspen): add support for configurable platform's CPU topology
- Add support for passing build time platform's CPU topology, which
defines the number of clusters and CPUs in the platform.
- Adjust the platform's power domain topology based on the passed
build time topology. If no build time topology was provided,
default topology will be used.
Change-Id: Ic80b308ab6d4c98139723021566d54be02b7d125
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
Signed-off-by: David Hu <david.hu2@arm.com>
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| ba4814b8 | 19-Mar-2025 |
Jun Wu <jun.wu@arm.com> |
feat(rdaspen): scmi gracefully shutdown system
In RD-Aspen, RSE shall be responsible for system shutdown. When TF-A
send a graceful SCMI system power set command to SCP, SCP will not
execute the shu
feat(rdaspen): scmi gracefully shutdown system
In RD-Aspen, RSE shall be responsible for system shutdown. When TF-A
send a graceful SCMI system power set command to SCP, SCP will not
execute the shutdown but notify RSE runtime.
RD-Aspen enable the graceful flag of css_scp_system_off in
platform.mk.
Change-Id: I80967e1d2e85193dd98f626e4c729ac722251a53
Signed-off-by: Jun Wu <jun.wu@arm.com>
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| d69c3b1c | 28-Feb-2025 |
Amr Mohamed <amr.mohamed@arm.com> |
feat(rdaspen): add DSU support
- Enable use of the DSU driver through the `USE_DSU_DRIVER` flag.
This configures DSU power-down and power settings, using the
default reset values defined in the
feat(rdaspen): add DSU support
- Enable use of the DSU driver through the `USE_DSU_DRIVER` flag.
This configures DSU power-down and power settings, using the
default reset values defined in the DSU-120AE TRM.
- Enable the `PRESERVE_DSU_PMU_REGS` flag to save and restore DSU
cluster PMU registers across cluster power cycles.
Change-Id: I7f820981cd164a689324a525b506c2979bddb572
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
Signed-off-by: Meet Patel <meet.patel2@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
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| 287e24f5 | 19-May-2025 |
Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com> |
feat(rdaspen): enable tbb on rd-aspen platform
Enable Trusted board boot on RD-Aspen platform.
Included the non-volatile(NV) memory region, to
ensure rollback protection.
Added Mbed TLS library in
feat(rdaspen): enable tbb on rd-aspen platform
Enable Trusted board boot on RD-Aspen platform.
Included the non-volatile(NV) memory region, to
ensure rollback protection.
Added Mbed TLS library initialization for MbedTLS
library.
Change-Id: I7940952c152b0243a91b38804cf16d3050ec2d4b
Signed-off-by: Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
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| 26384969 | 29-Jul-2024 |
Divin Raj <divin.raj@arm.com> |
feat(rd1ae): enabling Trusted Board Boot(TBB) for RD-1 AE
In this commit, Trusted Board Boot has been enabled for the RD-1 AE
platform, and the non-volatile counter remains at the default
values sin
feat(rd1ae): enabling Trusted Board Boot(TBB) for RD-1 AE
In this commit, Trusted Board Boot has been enabled for the RD-1 AE
platform, and the non-volatile counter remains at the default
values since the non-volatile counter is read-only for Arm
development platforms.
Signed-off-by: Divin Raj <divin.raj@arm.com>
Change-Id: I2e1072101e56da0e474d2a3e9802e5d65a77fd55
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