feat(versal2): add PM support for 1-cluster 4-core topology

Add PM node IDs for Core 2 and Core 3 of Cluster 0.

Add new pm_proc structure to support the 1 Cluster 4 cores topology and
select the pm

feat(versal2): add PM support for 1-cluster 4-core topology

Add PM node IDs for Core 2 and Core 3 of Cluster 0.

Add new pm_proc structure to support the 1 Cluster 4 cores topology and
select the pm_proc table dynamically based on topology.

Update APU_PCIL core index calculation logic to support 1-cluster
4-core topology.

Change-Id: I14ba4a2caa9a9872adaa44a78dc288ec49cbcc89
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>

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feat(versal2): add static topology via build arg

Introduce VERSAL2_VARIANT build argument to select the CPU topology
at compile time. When VERSAL2_VARIANT=14 is passed:

- PLATFORM_CLUSTER_COUNT is

feat(versal2): add static topology via build arg

Introduce VERSAL2_VARIANT build argument to select the CPU topology
at compile time. When VERSAL2_VARIANT=14 is passed:

- PLATFORM_CLUSTER_COUNT is set to 1 and
PLATFORM_CORE_COUNT_PER_CLUSTER to 4, yielding 4 total cores.

The default configuration uses VERSAL2_VARIANT=42, providing
4 clusters with 2 cores each (8 total cores).

Platform cluster and core limits and the static power-domain tree
layout follow the selected variant.

The versal2-2vm3654 variant has a single CPU cluster of four cores
(VERSAL2_VARIANT=14) instead of the general-purpose Versal Gen 2
topology (4 clusters × 2 cores, VERSAL2_VARIANT=42).

Change-Id: Ib22c87ae58cc87da726d36a0f8370ecd97598bf5
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(versal2): use 64-bit macros for BL31 checks

BL31_BASE and BL31_LIMIT are used for BL31 address range
validation during platform checks.

Using U() produces 32-bit constants, which can truncate
u

fix(versal2): use 64-bit macros for BL31 checks

BL31_BASE and BL31_LIMIT are used for BL31 address range
validation during platform checks.

Using U() produces 32-bit constants, which can truncate
upper address bits and cause incorrect comparisons on
AArch64 systems.

Update these macros to use UL() so the constants are
64-bit and type-consistent.

Change-Id: Idae2d3e3874258a60b859b65e09c2d03693c086a
Signed-off-by: Sai Varun Venkatapuram <saivarun.venkatapuram@amd.com>

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Merge changes from topic "amd_feat_dyn_core_clust" into integration

* changes:
feat(versal2): update plat psci based on dynamic core and cluster
feat(versal2): add dynamic fetching of core and c

Merge changes from topic "amd_feat_dyn_core_clust" into integration

* changes:
feat(versal2): update plat psci based on dynamic core and cluster
feat(versal2): add dynamic fetching of core and cluster
refactor(xilinx): promote map/unmap helpers to public scope
feat(versal2): use runtime core/cluster variables for dyn topology

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feat(versal2): update plat psci based on dynamic core and cluster

Update the psci logic under TFA_NO_PM which checks for core and
cluster counts based on the dynamic core and cluster information
ret

feat(versal2): update plat psci based on dynamic core and cluster

Update the psci logic under TFA_NO_PM which checks for core and
cluster counts based on the dynamic core and cluster information
retrieved from the DT blob.

Change-Id: If32f4a114099eca5d8961ff89e481257ebca49c1
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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feat(versal2): add dynamic fetching of core and cluster

Add dynamic fetching of core and cluster information from device tree
blob and on failure fallback to default configurations of Versal Gen 2.

feat(versal2): add dynamic fetching of core and cluster

Add dynamic fetching of core and cluster information from device tree
blob and on failure fallback to default configurations of Versal Gen 2.

Change-Id: Ide03f8a412f7155c0c85627be4fd1e0064863fc9
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(versal2): add prototype for external linkage

MISRA violation C2012-8.4:
A compatible declaration shall be visible when an object or function
with
external linkage is defined.
Added visible proto

fix(versal2): add prototype for external linkage

MISRA violation C2012-8.4:
A compatible declaration shall be visible when an object or function
with
external linkage is defined.
Added visible prototype to fix this violation.

Change-Id: Ia4b2b8077944b90c36d848e83faadbf6d2f8a0e9
Signed-off-by: Sai Varun Venkatapuram <saivarun.venkatapuram@amd.com>

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Merge changes from topic "amd_custompkg_infra" into integration

* changes:
fix(versal2): remove SCMI drivers in NO PM configuration
feat(amd): custom package linker infra
chore(versal2): make

Merge changes from topic "amd_custompkg_infra" into integration

* changes:
fix(versal2): remove SCMI drivers in NO PM configuration
feat(amd): custom package linker infra
chore(versal2): make TFA_NO_PM configurable with default value
feat(amd): support multiple custom packages

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fix(versal2): remove SCMI drivers in NO PM configuration

Remove SCMI message driver and related sources when TFA_NO_PM=1,
as SCMI functionality is only relevant when power management is
enabled.

Wh

fix(versal2): remove SCMI drivers in NO PM configuration

Remove SCMI message driver and related sources when TFA_NO_PM=1,
as SCMI functionality is only relevant when power management is
enabled.

When TF-A is built without PM support (TFA_NO_PM=1), the platform
only needs basic PSCI support. The SCMI server implementation and
scmi-msg drivers are unnecessary in this configuration and should
be excluded from the build.

Changes:
- Remove SCMI-related source files from BL31_SOURCES in NO PM path
- Delete scmi.c implementation (clock, reset, power domain stubs)
- Keep only minimal plat_psci.c for basic PSCI functionality

This reduces binary size and removes unused code paths when SCMI
services are not required.

Change-Id: I33397b1fa32e309728042b1bdba07aa6ad02c844
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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fix(versal2): update IRQ_MAX for SDIO interrupts

IRQ_MAX is defined as 200U but the irq_to_pm_node_idx()
function handles IRQ numbers up to 220 for SDIO devices
(IRQ 218 for SDIO_0 and IRQ 220 for S

fix(versal2): update IRQ_MAX for SDIO interrupts

IRQ_MAX is defined as 200U but the irq_to_pm_node_idx()
function handles IRQ numbers up to 220 for SDIO devices
(IRQ 218 for SDIO_0 and IRQ 220 for SDIO_1).

This mismatch causes a runtime assertion failure when SDIO
interrupts are processed, preventing proper SDIO device power
management.

Update IRQ_MAX to 220U to accommodate the highest IRQ number
actually handled by the platform.

Change-Id: Icc78e4325750c69d8b50423675f256314993ecec
Signed-off-by: Devanshi Chauhan <Devanshi.ChauhanAlpeshbhai@amd.com>

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feat(versal2): support alternate core as primary (non-cpu0)

Primary core was hardcoded to CPU0, causing a panic when another
core booted first.
Update logic to allow any booting core to become the p

feat(versal2): support alternate core as primary (non-cpu0)

Primary core was hardcoded to CPU0, causing a panic when another
core booted first.
Update logic to allow any booting core to become the primary and
gate secondary core startup inline to existing implementation for
secondary cores.

Change-Id: I6a5d76f23d4d4c4139d95bbaf55edf1244f2dbfe
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(versal2): align comment about invalid console selection

Error message should be aligned actual symbol used for console section
which has been changed by commit 2333ab4cd214 ("fix(versal2): renam

fix(versal2): align comment about invalid console selection

Error message should be aligned actual symbol used for console section
which has been changed by commit 2333ab4cd214 ("fix(versal2): rename
console build arg to generic").

Change-Id: I230892875a6343ca8ffc55e0fac251f6586cf3f4
Signed-off-by: Michal Simek <michal.simek@amd.com>

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feat(xilinx): use common SECURE/NON_SECURE macro

Remove platform-specific macro definitions such as SECURE_FLAG and
NON_SECURE_FLAG, and replace them with the common macros SECURE and
NON_SECURE acr

feat(xilinx): use common SECURE/NON_SECURE macro

Remove platform-specific macro definitions such as SECURE_FLAG and
NON_SECURE_FLAG, and replace them with the common macros SECURE and
NON_SECURE across all AMD-Xilinx platforms.

Change-Id: I95465e29ac8a9370da135c2113203c3206ecfec0
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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feat(versal2): add hooks for mmap and early setup

Add early setup hooks through custom_early_setup() and provide a
mechanism to support custom memory mapping, including the extension
of the memory m

feat(versal2): add hooks for mmap and early setup

Add early setup hooks through custom_early_setup() and provide a
mechanism to support custom memory mapping, including the extension
of the memory map via custom_mmap_add(). This change may also
require alignment of the MAX_XLAT_TABLE and MAX_XLAT_TABLES macros.
These can be defined within the custom_pkg.mk makefile as follows:

MAX_MMAP_REGIONS := XY
$(eval $(call add_define,MAX_MMAP_REGIONS))
MAX_XLAT_TABLES := XZ
$(eval $(call add_define,MAX_XLAT_TABLES))

If PLATFORM_STACK_SIZE is not already defined, a default value
should be used. This allows for configurability of the stack size
across different interfaces, such as custom packages. The
custom_early_setup() function enables early low-level operations
to bring the system into a correct state. Support for a custom
SiP service is also added. A basic implementation of
custom_smc_handler() is provided by the platform, while the actual
definition is expected to be supplied by the custom package. This
feature is designed for use by external libraries, such as those
that require status checking. This code introduces a generic
framework for integrating custom logic via the
$(CUSTOM_PKG_PATH)/custom_pkg.mk makefile, including
optional support for custom SMC functionality, which is determined
by the custom package.

Change-Id: I40281acf2dc48be43471b8642e2ab1a93b1cf8f6
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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refactor(versal2): add tfa_no_pm flag for scmi

Added the TFA_NO_PM flag in the SCMI file and guarded SCMI
functionality with if conditions. When TFA_NO_PM is set to 0
(default), Platform Management

refactor(versal2): add tfa_no_pm flag for scmi

Added the TFA_NO_PM flag in the SCMI file and guarded SCMI
functionality with if conditions. When TFA_NO_PM is set to 0
(default), Platform Management is enabled. When set to 1, Platform
Management is disabled. This allows the generic SCMI driver to be
used in non-PM scenarios while maintaining compatibility with
conforming power management interfaces.

Change-Id: I4f6483e2c8a322ecb41e523bc03a351af4a2cb6b
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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fix(versal2): align IOU_SCNTR base address macro name with other platforms

Renamed the IOU_SCNTR base address macro to match the naming
convention used in Versal and Versal NET. This ensures
consist

fix(versal2): align IOU_SCNTR base address macro name with other platforms

Renamed the IOU_SCNTR base address macro to match the naming
convention used in Versal and Versal NET. This ensures
consistency across platforms and enables the use of a common
function for getting and setting the system counter-timer
frequency.

Change-Id: I257a1086d77350858d63859b0fbe6e2b47deb9e5
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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feat(versal2): add bufferless IPI Support

Versal Gen 2 SOC has same IPI mapping as Versal NET SOC.

Ports the bufferless Versal NET IPI mapping to
Versal Gen 2.

Change-Id: I1dc11c8473c390a517fdd3a9

feat(versal2): add bufferless IPI Support

Versal Gen 2 SOC has same IPI mapping as Versal NET SOC.

Ports the bufferless Versal NET IPI mapping to
Versal Gen 2.

Change-Id: I1dc11c8473c390a517fdd3a9e4fc35dc5563792b
Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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chore(versal2): use BIT_32() macro

Use BIT_32() macro for readability for Versal Gen 2 IPI Bit positions.

Change-Id: I69718b22de890519e906be185f593b4fd9df1be5
Signed-off-by: Ben Levinsky <ben.levin

chore(versal2): use BIT_32() macro

Use BIT_32() macro for readability for Versal Gen 2 IPI Bit positions.

Change-Id: I69718b22de890519e906be185f593b4fd9df1be5
Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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