1 /* 2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <drivers/delay_timer.h> 14 #include <lib/mmio.h> 15 #include <lib/utils_def.h> 16 #include <plat/common/platform.h> 17 18 #include <sunxi_cpucfg.h> 19 #include <sunxi_mmap.h> 20 #include <sunxi_private.h> 21 22 #ifndef SUNXI_CPUIDLE_EN_REG 23 #include <core_off_arisc.h> 24 #endif 25 26 static void sunxi_cpu_disable_power(unsigned int cluster, unsigned int core) 27 { 28 if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0xff) 29 return; 30 31 VERBOSE("PSCI: Disabling power to cluster %d core %d\n", cluster, core); 32 33 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xff); 34 } 35 36 static void sunxi_cpu_enable_power(unsigned int cluster, unsigned int core) 37 { 38 if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0) 39 return; 40 41 VERBOSE("PSCI: Enabling power to cluster %d core %d\n", cluster, core); 42 43 /* Power enable sequence from original Allwinner sources */ 44 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xfe); 45 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xf8); 46 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xe0); 47 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x80); 48 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x00); 49 } 50 51 /* We can't turn ourself off like this, but it works for other cores. */ 52 static void sunxi_cpu_off(u_register_t mpidr) 53 { 54 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); 55 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); 56 57 VERBOSE("PSCI: Powering off cluster %d core %d\n", cluster, core); 58 59 /* Deassert DBGPWRDUP */ 60 mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); 61 /* Activate the core output clamps, but not for core 0. */ 62 if (core != 0) 63 mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core)); 64 /* Assert CPU power-on reset */ 65 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); 66 /* Remove power from the CPU */ 67 sunxi_cpu_disable_power(cluster, core); 68 } 69 70 void sunxi_cpu_power_off_self(void) 71 { 72 u_register_t mpidr = read_mpidr(); 73 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); 74 75 /* Simplifies assembly, all SoCs so far are single cluster anyway. */ 76 assert(MPIDR_AFFLVL1_VAL(mpidr) == 0); 77 78 #ifdef SUNXI_CPUIDLE_EN_REG 79 /* Enable the CPUIDLE hardware (only really needs to be done once). */ 80 mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0x16aa0000); 81 mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0xaa160001); 82 83 /* Trigger power off for this core. */ 84 mmio_write_32(SUNXI_CORE_CLOSE_REG, BIT_32(core)); 85 #else 86 /* 87 * If we are supposed to turn ourself off, tell the arisc SCP 88 * to do that work for us. The code expects the core mask to be 89 * patched into the first instruction. 90 */ 91 sunxi_execute_arisc_code(arisc_core_off, sizeof(arisc_core_off), 92 BIT_32(core)); 93 #endif 94 } 95 96 void sunxi_cpu_on(u_register_t mpidr) 97 { 98 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); 99 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); 100 101 VERBOSE("PSCI: Powering on cluster %d core %d\n", cluster, core); 102 103 /* Assert CPU core reset */ 104 mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); 105 /* Assert CPU power-on reset */ 106 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); 107 /* Set CPU to start in AArch64 mode */ 108 mmio_setbits_32(SUNXI_CPUCFG_CLS_CTRL_REG0(cluster), BIT(24 + core)); 109 /* Apply power to the CPU */ 110 sunxi_cpu_enable_power(cluster, core); 111 /* Release the core output clamps */ 112 mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core)); 113 /* Deassert CPU power-on reset */ 114 mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); 115 /* Deassert CPU core reset */ 116 mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); 117 /* Assert DBGPWRDUP */ 118 mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); 119 } 120 121 void sunxi_cpu_power_off_others(void) 122 { 123 u_register_t self = read_mpidr(); 124 unsigned int cluster; 125 unsigned int core; 126 127 for (cluster = 0; cluster < PLATFORM_CLUSTER_COUNT; ++cluster) { 128 for (core = 0; core < PLATFORM_MAX_CPUS_PER_CLUSTER; ++core) { 129 u_register_t mpidr = (cluster << MPIDR_AFF1_SHIFT) | 130 (core << MPIDR_AFF0_SHIFT) | 131 BIT(31); 132 if (mpidr != self) 133 sunxi_cpu_off(mpidr); 134 } 135 } 136 } 137