feat(handoff): introduce firmware handoff library

Add transfer list APIs and firmware handoff build option.

Change-Id: I68a0ace22c7e50fcdacd101eb76b271d7b76d8ff
Signed-off-by: Raymond Mao <raymond.

feat(handoff): introduce firmware handoff library

Add transfer list APIs and firmware handoff build option.

Change-Id: I68a0ace22c7e50fcdacd101eb76b271d7b76d8ff
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>

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fix(cpus): update the fix for Cortex-A78AE erratum 1941500

This patch fixes the mitigation for erratum 1941500 for the
Cortex-A78AE CPUs. The right fix is to set the bit 8, whereas
the current code

fix(cpus): update the fix for Cortex-A78AE erratum 1941500

This patch fixes the mitigation for erratum 1941500 for the
Cortex-A78AE CPUs. The right fix is to set the bit 8, whereas
the current code clears it.

Reported-by: matthias.rosenfelder@nio.io
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ib7c3fddd567eeae6204756377e0f77a573c0a911

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fix(cpus): workaround for Neoverse V2 erratum 2743011

Neoverse V2 erratum 2743011 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
set CPUACTLR5_EL

fix(cpus): workaround for Neoverse V2 erratum 2743011

Neoverse V2 erratum 2743011 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
set CPUACTLR5_EL1[56:55] to 2'b01.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I0e06ca723a1cce51fb027b7160f3dd06a4c93e64

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fix(cpus): workaround for Neoverse V2 erratum 2779510

Neoverse V2 erratum 2779510 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
set bit[47] of C

fix(cpus): workaround for Neoverse V2 erratum 2779510

Neoverse V2 erratum 2779510 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
set bit[47] of CPUACTLR3_EL1 which might have a small impact on
power and negligible impact on performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I6d937747bdcbf2913a64c4037f99918cbc466e80

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fix(cpus): workaround for Neoverse V2 erratum 2719105

Neoverse V2 erratum 2719105 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.

The erratum is avoided by setting CP

fix(cpus): workaround for Neoverse V2 erratum 2719105

Neoverse V2 erratum 2719105 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.

The erratum is avoided by setting CPUACTLR2_EL1[0] to 1 to force
PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations
to other PE caches. There might be a small performance degradation
to this workaround for certain workloads that share data.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Id026edcb7ee1ca93371ce0001d18f5a8282c49ba

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fix(cpus): workaround for Neoverse V2 erratum 2331132

Neoverse V2 erratum 2331132 is a Cat B erratum that applies to all
revisions <= r0p2 and is still open. The workaround is to write the
value 4'b

fix(cpus): workaround for Neoverse V2 erratum 2331132

Neoverse V2 erratum 2331132 is a Cat B erratum that applies to all
revisions <= r0p2 and is still open. The workaround is to write the
value 4'b1001 to the PF_MODE bits in the IMP_CPUECTLR2_EL1 register
which will place the data prefetcher in the most conservative mode
instead of disabling it.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ic6c76375df465a4ad2e20dd7add7037477d973c1

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Merge changes from topic "sm/errata_X3" into integration

* changes:
fix(cpus): workaround for Cortex-X3 erratum 2742421
feat(errata_abi): add support for Cortex-X3

fix(cpus): workaround for Cortex-X3 erratum 2742421

Cortex-X3 erratum 2742421 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL1[56

fix(cpus): workaround for Cortex-X3 erratum 2742421

Cortex-X3 erratum 2742421 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL1[56:55] to 2'b01.

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Change-Id: Idadd323e419739fe909b9b68ea2dbe857846666b

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Merge "fix(cpus): workaround for Neoverse N2 erratum 2009478" into integration

Merge "feat(cpufeat): initialize HFG*_EL2 registers" into integration

fix(cpus): workaround for Neoverse N2 erratum 2009478

Neoverse N2 erratum 2009478 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1. The workaround is to clear
the ED bit for all

fix(cpus): workaround for Neoverse N2 erratum 2009478

Neoverse N2 erratum 2009478 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1. The workaround is to clear
the ED bit for all core error records before setting the PWRDN_EN
bit in CPUPWRCTLR_EL1 to request a power down.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ic5ef58c9e795b90026af1d2b09edc0eea3ceee51

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Merge "feat(cpus): add support for Nevis CPU" into integration

feat(cpus): add support for Nevis CPU

Adding basic CPU library code to support Nevis CPU

Change-Id: I399cc9b7b2d907b02b76ea2a3e5abb54e28fbf6c
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.co

feat(cpus): add support for Nevis CPU

Adding basic CPU library code to support Nevis CPU

Change-Id: I399cc9b7b2d907b02b76ea2a3e5abb54e28fbf6c
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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Merge changes from topic "sm_bk/errata_refactor" into integration

* changes:
refactor(cpus): convert the Cortex-A57 to use cpu helpers
refactor(cpus): convert the Cortex-A57 to use the errata fr

Merge changes from topic "sm_bk/errata_refactor" into integration

* changes:
refactor(cpus): convert the Cortex-A57 to use cpu helpers
refactor(cpus): convert the Cortex-A57 to use the errata framework
refactor(cpus): reorder Cortex-A57 errata by ascending order
refactor(cpus): add Cortex-A57 errata framework information
refactor(cpus): convert the Cortex-A53 to use cpu helpers
refactor(cpus): convert the Cortex-A53 to use the errata framework
refactor(cpus): reorder Cortex-A53 errata by ascending order

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refactor(cpus): convert the Cortex-A57 to use cpu helpers

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1cc10fa91cb9c837386144249dafeb6178d5866e

refactor(cpus): convert the Cortex-A57 to use the errata framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cp

refactor(cpus): convert the Cortex-A57 to use the errata framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive

It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.

At this point the binary output of all errata was checked with the
script from commit 19136. All reported discrepancies involve errata
with no workaround in the cpu file or errata that did not previously
have a workaround function and now do. The non temporal hint erratum has
been converted to a numeric erratum.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ib321ab01362c5954fe78e7349229c1437b3da847

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refactor(cpus): reorder Cortex-A57 errata by ascending order

Errata report order is enforced to be in ascending order. To achieve
this with the errata framework this has to be done at the definition

refactor(cpus): reorder Cortex-A57 errata by ascending order

Errata report order is enforced to be in ascending order. To achieve
this with the errata framework this has to be done at the definition
level.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ia98976797fc0811f30c7dbf714e94b36e3c2263e

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refactor(cpus): add Cortex-A57 errata framework information

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ic435b8d42639454fabb587ead44f646f7285cc40

refactor(cpus): convert the Cortex-A53 to use cpu helpers

Also, convert checker functions of errata which are enabled for all cpu
revisions to report correctly in preparation of the errata ABI.

Alt

refactor(cpus): convert the Cortex-A53 to use cpu helpers

Also, convert checker functions of errata which are enabled for all cpu
revisions to report correctly in preparation of the errata ABI.

Although the script from commit 250919 was used to check that errata
code did not change, this CPU only loosely adhered to convention and its
output was not particularly useful. Nevertheless, the discrepancies were
manually verified. All errata have been checked that they get invoked.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I988db6e7b6d1732f1d2258dbdf945cb475781894

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refactor(cpus): convert the Cortex-A53 to use the errata framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cp

refactor(cpus): convert the Cortex-A53 to use the errata framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive

It is important to note that the errata workaround and checking
sequences remain unchanged and preserve their git blame.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I30556f438859d17f054cb6bc96f3069b40474b58

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refactor(cpus): reorder Cortex-A53 errata by ascending order

Errata report order is enforced to be in ascending order. To achieve
this with the errata framework this has to be done at the definition

refactor(cpus): reorder Cortex-A53 errata by ascending order

Errata report order is enforced to be in ascending order. To achieve
this with the errata framework this has to be done at the definition
level.

Also rename the disable_non_temporal_hint to its erratum number to
conform to convention.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Id474872afebf361ab3d21c454ab3624db8354045

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fix(cpus): check for SME presence in Gelas

The original powerdown function for Gelas included SME disabling
instructions but did not check for the presence of SME before disabling.
This could lead t

fix(cpus): check for SME presence in Gelas

The original powerdown function for Gelas included SME disabling
instructions but did not check for the presence of SME before disabling.
This could lead to unexpected beaviors. This patch adds that check so
the feature is disabled only if it is present.

Change-Id: I582db53a6669317620e4f72a3eac87525897d3d0
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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refactor(cm): move remaining EL2 save/restore into C

MTE and common system registers are the last remaining EL2 save/restores
in assembly. Convert them to C, like all the others.

Signed-off-by: Boy

refactor(cm): move remaining EL2 save/restore into C

MTE and common system registers are the last remaining EL2 save/restores
in assembly. Convert them to C, like all the others.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: If690f792e70b97fd4b4cd5f43847a71719b128f1

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Merge "feat(cpus): add support for Gelas CPU" into integration

feat(cpus): add support for Gelas CPU

This patch adds the necessary CPU library code to support the Gelas CPU

Change-Id: I13ec4a8bb7055c1ebd0796a4a1378983d930fcb3
Signed-off-by: Juan Pablo Conde <j

feat(cpus): add support for Gelas CPU

This patch adds the necessary CPU library code to support the Gelas CPU

Change-Id: I13ec4a8bb7055c1ebd0796a4a1378983d930fcb3
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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