1/* 2 * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <common/debug.h> 10#include <cortex_a53.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include <lib/cpus/errata.h> 14 15 /* --------------------------------------------- 16 * Disable L1 data cache and unified L2 cache 17 * --------------------------------------------- 18 */ 19func cortex_a53_disable_dcache 20 mrs x1, sctlr_el3 21 bic x1, x1, #SCTLR_C_BIT 22 msr sctlr_el3, x1 23 isb 24 ret 25endfunc cortex_a53_disable_dcache 26 27 /* --------------------------------------------- 28 * Disable intra-cluster coherency 29 * --------------------------------------------- 30 */ 31func cortex_a53_disable_smp 32 mrs x0, CORTEX_A53_ECTLR_EL1 33 bic x0, x0, #CORTEX_A53_ECTLR_SMP_BIT 34 msr CORTEX_A53_ECTLR_EL1, x0 35 isb 36 dsb sy 37 ret 38endfunc cortex_a53_disable_smp 39 40/* Due to the nature of the errata it is applied unconditionally when chosen */ 41check_erratum_custom_start cortex_a53, ERRATUM(819472) 42#if ERRATA_A53_819472 43 mov x0, #ERRATA_APPLIES 44 ret 45#else 46 mov x1, #0x01 47 b cpu_rev_var_ls 48#endif 49check_erratum_custom_end cortex_a53, ERRATUM(819472) 50 51/* erratum workaround is interleaved with generic code */ 52add_erratum_entry cortex_a53, ERRATUM(819472), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET 53 54/* Due to the nature of the errata it is applied unconditionally when chosen */ 55check_erratum_custom_start cortex_a53, ERRATUM(824069) 56#if ERRATA_A53_824069 57 mov x0, #ERRATA_APPLIES 58 ret 59#else 60 mov x1, #0x02 61 b cpu_rev_var_ls 62#endif 63check_erratum_custom_end cortex_a53, ERRATUM(824069) 64 65/* erratum workaround is interleaved with generic code */ 66add_erratum_entry cortex_a53, ERRATUM(824069), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET 67 68workaround_reset_start cortex_a53, ERRATUM(826319), ERRATA_A53_826319 69 mrs x1, CORTEX_A53_L2ACTLR_EL1 70 bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN 71 orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH 72 msr CORTEX_A53_L2ACTLR_EL1, x1 73workaround_reset_end cortex_a53, ERRATUM(826319) 74 75check_erratum_ls cortex_a53, ERRATUM(826319), CPU_REV(0, 2) 76 77/* Due to the nature of the errata it is applied unconditionally when chosen */ 78check_erratum_custom_start cortex_a53, ERRATUM(827319) 79#if ERRATA_A53_827319 80 mov x0, #ERRATA_APPLIES 81 ret 82#else 83 mov x1, #0x02 84 b cpu_rev_var_ls 85#endif 86check_erratum_custom_end cortex_a53, ERRATUM(827319) 87 88/* erratum workaround is interleaved with generic code */ 89add_erratum_entry cortex_a53, ERRATUM(827319), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET 90 91check_erratum_custom_start cortex_a53, ERRATUM(835769) 92 cmp x0, #0x04 93 b.hi errata_not_applies 94 /* 95 * Fix potentially available for revisions r0p2, r0p3 and r0p4. 96 * If r0p2, r0p3 or r0p4; check for fix in REVIDR, else exit. 97 */ 98 cmp x0, #0x01 99 mov x0, #ERRATA_APPLIES 100 b.ls exit_check_errata_835769 101 /* Load REVIDR. */ 102 mrs x1, revidr_el1 103 /* If REVIDR[7] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */ 104 tbz x1, #7, exit_check_errata_835769 105errata_not_applies: 106 mov x0, #ERRATA_NOT_APPLIES 107exit_check_errata_835769: 108 ret 109check_erratum_custom_end cortex_a53, ERRATUM(835769) 110 111/* workaround at build time */ 112add_erratum_entry cortex_a53, ERRATUM(835769), ERRATA_A53_835769, NO_APPLY_AT_RESET 113 114 /* 115 * Disable the cache non-temporal hint. 116 * 117 * This ignores the Transient allocation hint in the MAIR and treats 118 * allocations the same as non-transient allocation types. As a result, 119 * the LDNP and STNP instructions in AArch64 behave the same as the 120 * equivalent LDP and STP instructions. 121 */ 122workaround_reset_start cortex_a53, ERRATUM(836870), ERRATA_A53_836870 | A53_DISABLE_NON_TEMPORAL_HINT 123 mrs x1, CORTEX_A53_CPUACTLR_EL1 124 orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_DTAH 125 msr CORTEX_A53_CPUACTLR_EL1, x1 126workaround_reset_end cortex_a53, ERRATUM(836870) 127 128check_erratum_ls cortex_a53, ERRATUM(836870), CPU_REV(0, 3) 129 130check_erratum_custom_start cortex_a53, ERRATUM(843419) 131 mov x1, #ERRATA_APPLIES 132 mov x2, #ERRATA_NOT_APPLIES 133 cmp x0, #0x04 134 csel x0, x1, x2, ls 135 /* 136 * Fix potentially available for revision r0p4. 137 * If r0p4 check for fix in REVIDR, else exit. 138 */ 139 b.ne exit_check_errata_843419 140 /* Load REVIDR. */ 141 mrs x3, revidr_el1 142 /* If REVIDR[8] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */ 143 tbz x3, #8, exit_check_errata_843419 144 mov x0, x2 145exit_check_errata_843419: 146 ret 147check_erratum_custom_end cortex_a53, ERRATUM(843419) 148 149/* workaround at build time */ 150add_erratum_entry cortex_a53, ERRATUM(843419), ERRATA_A53_843419, NO_APPLY_AT_RESET 151 152 /* 153 * Earlier revisions of the core are affected as well, but don't 154 * have the chicken bit in the CPUACTLR register. It is expected that 155 * the rich OS takes care of that, especially as the workaround is 156 * shared with other erratas in those revisions of the CPU. 157 */ 158workaround_reset_start cortex_a53, ERRATUM(855873), ERRATA_A53_855873 159 mrs x1, CORTEX_A53_CPUACTLR_EL1 160 orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_ENDCCASCI 161 msr CORTEX_A53_CPUACTLR_EL1, x1 162workaround_reset_end cortex_a53, ERRATUM(855873) 163 164check_erratum_hs cortex_a53, ERRATUM(855873), CPU_REV(0, 3) 165 166check_erratum_chosen cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924 167 168/* erratum has no workaround in the cpu. Generic code must take care */ 169add_erratum_entry cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924, NO_APPLY_AT_RESET 170 171cpu_reset_func_start cortex_a53 172 /* --------------------------------------------- 173 * Enable the SMP bit. 174 * --------------------------------------------- 175 */ 176 mrs x0, CORTEX_A53_ECTLR_EL1 177 orr x0, x0, #CORTEX_A53_ECTLR_SMP_BIT 178 msr CORTEX_A53_ECTLR_EL1, x0 179cpu_reset_func_end cortex_a53 180 181func cortex_a53_core_pwr_dwn 182 mov x18, x30 183 184 /* --------------------------------------------- 185 * Turn off caches. 186 * --------------------------------------------- 187 */ 188 bl cortex_a53_disable_dcache 189 190 /* --------------------------------------------- 191 * Flush L1 caches. 192 * --------------------------------------------- 193 */ 194 mov x0, #DCCISW 195 bl dcsw_op_level1 196 197 /* --------------------------------------------- 198 * Come out of intra cluster coherency 199 * --------------------------------------------- 200 */ 201 mov x30, x18 202 b cortex_a53_disable_smp 203endfunc cortex_a53_core_pwr_dwn 204 205func cortex_a53_cluster_pwr_dwn 206 mov x18, x30 207 208 /* --------------------------------------------- 209 * Turn off caches. 210 * --------------------------------------------- 211 */ 212 bl cortex_a53_disable_dcache 213 214 /* --------------------------------------------- 215 * Flush L1 caches. 216 * --------------------------------------------- 217 */ 218 mov x0, #DCCISW 219 bl dcsw_op_level1 220 221 /* --------------------------------------------- 222 * Disable the optional ACP. 223 * --------------------------------------------- 224 */ 225 bl plat_disable_acp 226 227 /* --------------------------------------------- 228 * Flush L2 caches. 229 * --------------------------------------------- 230 */ 231 mov x0, #DCCISW 232 bl dcsw_op_level2 233 234 /* --------------------------------------------- 235 * Come out of intra cluster coherency 236 * --------------------------------------------- 237 */ 238 mov x30, x18 239 b cortex_a53_disable_smp 240endfunc cortex_a53_cluster_pwr_dwn 241 242errata_report_shim cortex_a53 243 244 /* --------------------------------------------- 245 * This function provides cortex_a53 specific 246 * register information for crash reporting. 247 * It needs to return with x6 pointing to 248 * a list of register names in ascii and 249 * x8 - x15 having values of registers to be 250 * reported. 251 * --------------------------------------------- 252 */ 253.section .rodata.cortex_a53_regs, "aS" 254cortex_a53_regs: /* The ascii list of register names to be reported */ 255 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", \ 256 "cpuactlr_el1", "" 257 258func cortex_a53_cpu_reg_dump 259 adr x6, cortex_a53_regs 260 mrs x8, CORTEX_A53_ECTLR_EL1 261 mrs x9, CORTEX_A53_MERRSR_EL1 262 mrs x10, CORTEX_A53_L2MERRSR_EL1 263 mrs x11, CORTEX_A53_CPUACTLR_EL1 264 ret 265endfunc cortex_a53_cpu_reg_dump 266 267declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ 268 cortex_a53_reset_func, \ 269 cortex_a53_core_pwr_dwn, \ 270 cortex_a53_cluster_pwr_dwn 271