| b52a3497 | 09-Jul-2025 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(psci): add missing curly braces" into integration |
| f05b4894 | 24-Apr-2024 |
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com> |
fix(el3-runtime): typecast operands to match data type
This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or o
fix(el3-runtime): typecast operands to match data type
This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
Replaced usage of 'unsigned int' with 'size_t' to ensure type
consistency and prevent assignment to a narrower or different
essential type.
Change-Id: I79501e216a04753ebd005d64375357b9332440d9
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
show more ...
|
| a540c456 | 08-Jul-2025 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(locks): add non-blocking spinlock_try() API" into integration |
| 6eafc060 | 04-Mar-2025 |
Boyan Karatotev <boyan.karatotev@arm.com> |
refactor(cm): gather per-world context management to the same place
The per-world calls are disparate - they get called in different places,
are guarded in different ways, and the code is apart.
Si
refactor(cm): gather per-world context management to the same place
The per-world calls are disparate - they get called in different places,
are guarded in different ways, and the code is apart.
Since they just need to be called once at boot, add a function that we
can call from BL31 and be done with it.
Change-Id: Id0ade302e35f2b00ca37c552a53038942ab7b58e
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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|
| e8c3fddb | 24-Apr-2025 |
Prasad Kummari <prasad.kummari@amd.com> |
fix(psci): initialise variable to default zero
This corrects the MISRA violation C2012-9.1:
The value of an object with automatic storage duration shall
not be read before it has been set.Initializ
fix(psci): initialise variable to default zero
This corrects the MISRA violation C2012-9.1:
The value of an object with automatic storage duration shall
not be read before it has been set.Initialized the variable
to default value zero.
Change-Id: Ib3a2a853b82ce3c3ba1f518705d7ac2e01130e37
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
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|
| f3d9e22a | 22-Apr-2025 |
Prasad Kummari <prasad.kummari@amd.com> |
fix(psci): add missing curly braces
This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement
shall be a compound-statement.Enclosed statement body w
fix(psci): add missing curly braces
This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement
shall be a compound-statement.Enclosed statement body within
the curly braces.
Change-Id: Ibd402a52e44e59d1c37613d8925aac8e115aa31c
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
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|
| f9274127 | 26-Jun-2025 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(cpus): workaround for Cortex-A710 erratum 1927200" into integration |
| b34be5df | 10-Apr-2025 |
Boyan Karatotev <boyan.karatotev@arm.com> |
fix(psci): do not modify higher levels for standby in OSI mode
The OSI mode for the CPU standby fast path updates the requested power
states incorrectly. psci_update_req_local_pwr_states() will not
fix(psci): do not modify higher levels for standby in OSI mode
The OSI mode for the CPU standby fast path updates the requested power
states incorrectly. psci_update_req_local_pwr_states() will not bother
saving level 0. It will also clamp the level it accesses to the
end_pwrlvl argument. Well, in the fast path, this argument is always 0
(as a condition of entering the fast path). The result is that it reads
the level 0 power state (retention) and writes it to the level 1 power
state, even though by definition, the fast path will not update higher
power levels.
The fix is to pass PLAT_MAX_PWR_LVL instead of target_pwrlvl to
psci_update_req_local_pwr_states(). However, doing that makes it
apparent that this call will not change anything and therefore there is
nothing to save - the level 0 power state is written by
psci_set_cpu_local_state(). So the save + restore are redundant. Remove
them to save on a bunch of work.
Another thing that is not considered is locking. No locks are held in
the fast path, so these updates are not safe.
Change-Id: Icc785df87b294b938b59705116369abd80ccf4da
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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|
| d90bb650 | 23-Jun-2025 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "build(handoff)!: switch to LibTL submodule" into integration |
| f6166f7f | 24-Apr-2024 |
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com> |
fix(psci): typecast operands to match data type
This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a dif
fix(psci): typecast operands to match data type
This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: Ic4a109cb55fdf9b60c8d26df68f61811b59a1a9f
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
show more ...
|
| b5d0740e | 13-May-2025 |
Harrison Mutai <harrison.mutai@arm.com> |
build(handoff)!: switch to LibTL submodule
Removes in-tree Transfer List implementation and updates all references
to use the external LibTL submodule. Updates include paths, Makefile
macros, and pl
build(handoff)!: switch to LibTL submodule
Removes in-tree Transfer List implementation and updates all references
to use the external LibTL submodule. Updates include paths, Makefile
macros, and platform integration logic to link with LibTL as a static
library.
If you cloned TF-A without the `--recurse-submodules` flag, you can
ensure that this submodule is present by running:
git submodule update --init --recursive
BREAKING-CHANGE: LibTL is now included in TF-A as a submodule.
Please run `git submodule update --init --recursive` if you encounter
issues after migrating to the latest version of TF-A.
Change-Id: I1fa31f7b730066c27985d968698e553b00b07c38
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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|
| e493b522 | 19-Jun-2025 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "perf(bl31): convert cpu_data fetching to C" into integration |
| d43b2ea6 | 18-Mar-2025 |
Boyan Karatotev <boyan.karatotev@arm.com> |
perf(bl31): convert cpu_data fetching to C
The assembly routines are opaque to the compiler and it can't inline
them. There is also no requirement for them to be called without a
stack - each of the
perf(bl31): convert cpu_data fetching to C
The assembly routines are opaque to the compiler and it can't inline
them. There is also no requirement for them to be called without a
stack - each of their calls has a stack available. So convert them to C
so that the compiler can do its inlining magic.
On AArch32 we need to be able to call _cpu_data from the entrypoint so
it has to stay as a slight exception.
We can also straighten out the type of the cpu_ops_ptr member so we
don't have to cast it everywhere.
Change-Id: I9c2939a955b396edf26b99ef36318eebeaab13e6
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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|
| 7554f1df | 17-Jun-2025 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes I1fae91a5,I54793492,I703f0e6e into integration
* changes:
fix(cpus): workaround for Cortex-A710 erratum 1917258
fix(cpus): workaround for Cortex-A710 erratum 1916945
fix(cpus): w
Merge changes I1fae91a5,I54793492,I703f0e6e into integration
* changes:
fix(cpus): workaround for Cortex-A710 erratum 1917258
fix(cpus): workaround for Cortex-A710 erratum 1916945
fix(cpus): workaround for Cortex-A710 erratum 1901946
show more ...
|
| cb2702c4 | 09-Jun-2025 |
John Powell <john.powell@arm.com> |
fix(cpus): workaround for Cortex-A710 erratum 1927200
Cortex-A710 erratum 1927200 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.
The fix is to insert DMB ST before
fix(cpus): workaround for Cortex-A710 erratum 1927200
Cortex-A710 erratum 1927200 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.
The fix is to insert DMB ST before acquire atomic instructions
without release semantics via instruction patching.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101
Change-Id: I53c4aa17c1c2dc85b68f17d58f93bb1ee6b3d488
Signed-off-by: John Powell <john.powell@arm.com>
show more ...
|
| 86822f24 | 15-May-2025 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(locks): add non-blocking spinlock_try() API
Add a non-blocking `spin_trylock()` function to the existing spinlock
implementation. This API attempts to acquire the lock and returns `1`
on succes
feat(locks): add non-blocking spinlock_try() API
Add a non-blocking `spin_trylock()` function to the existing spinlock
implementation. This API attempts to acquire the lock and returns `1`
on success or `0` if the lock is already held. It enables conditional
locking scenarios where blocking is undesirable.
Change-Id: I9483206952d1a34dc245ebf69e80c3645b658946
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| 935e0990 | 13-Jun-2025 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(psci): add API to get number of CPUs currently in ON state" into integration |
| addb93e0 | 12-Jun-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge "fix(rme): enable support for FEAT_D128 on Realm world" into integration |
| 34000665 | 12-Jun-2025 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(libc): add missing curly braces" into integration |
| a3effe0a | 10-Jun-2025 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
fix(rme): enable support for FEAT_D128 on Realm world
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I9a4431038968a260e1a4998d8a4f84a07768db74 |
| efc945f1 | 05-May-2025 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
feat(errata): implement workaround for DSU-120 erratum 2900952
DSU Erratum 2900952 is a Cat B erratum that applies to some
DSU-120 implementations of revision r2p0 and is fixed in r2p1.
This erratum
feat(errata): implement workaround for DSU-120 erratum 2900952
DSU Erratum 2900952 is a Cat B erratum that applies to some
DSU-120 implementations of revision r2p0 and is fixed in r2p1.
This erratum is fixed in certain implementations of r2p0 which can be
determined by reading the IMP_CLUSTERREVIDR_EL1[1] register field
where a set bit indicates that the erratum is fixed in this part.
The workaround is to set the CLUSTERACTLR_EL1 bits [21:20] to 0x3
which ignores CBusy from the system interconnect and
setting CLUSTERACTLR_EL1 bit [8] to 1 to assert CBusy from DSU to
all the cores when DSU is busy.
SDEN: https://developer.arm.com/documentation/SDEN-2453103/1200/?lang=en
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I87aa440ab5c35121aff703032f5cf7a62d0b0bb4
show more ...
|
| a7be2a57 | 29-May-2025 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(psci): add API to get number of CPUs currently in ON state
Introduce a new PSCI helper function `psci_num_cpus_running_on_safe()`
to return the number of CPUs that are currently in the ON state
feat(psci): add API to get number of CPUs currently in ON state
Introduce a new PSCI helper function `psci_num_cpus_running_on_safe()`
to return the number of CPUs that are currently in the ON state.
This API locks the PSCI power state data to ensure consistency and
is safe to call in concurrent environments.
This utility can assist components that need to reason about system
CPU activity or coordinate operations based on active CPUs.
Change-Id: Ie15aa4bd393a5f01e7cd80ae8a9b28707fde7c53
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| d91c4177 | 09-Jun-2025 |
John Powell <john.powell@arm.com> |
fix(cpus): workaround for Cortex-A710 erratum 1917258
Cortex-A710 erratum 1917258 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.
The workaround is to set CPUACTLR4
fix(cpus): workaround for Cortex-A710 erratum 1917258
Cortex-A710 erratum 1917258 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.
The workaround is to set CPUACTLR4_EL1[43]. This has no
performance impact.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101
Change-Id: I1fae91a5e3a8ecea255f0f0a481bfd6196a7db51
Signed-off-by: John Powell <john.powell@arm.com>
show more ...
|
| df067c0a | 09-Jun-2025 |
John Powell <john.powell@arm.com> |
fix(cpus): workaround for Cortex-A710 erratum 1916945
Cortex-A710 erratum 1916945 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.
The workaround is to set CPUECTLR_
fix(cpus): workaround for Cortex-A710 erratum 1916945
Cortex-A710 erratum 1916945 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.
The workaround is to set CPUECTLR_EL1[8]. This has a slight
performance impact.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101
Change-Id: I54793492c527928d7f266165a31b8613de838e69
Signed-off-by: John Powell <john.powell@arm.com>
show more ...
|
| 4467348b | 09-Jun-2025 |
John Powell <john.powell@arm.com> |
fix(cpus): workaround for Cortex-A710 erratum 1901946
Cortex-A710 erratum 1901946 is a Cat B erratum that applies
to revision r1p0 and is fixed in r2p0.
The workaround is to set CPUACTLR4_EL1[15].
fix(cpus): workaround for Cortex-A710 erratum 1901946
Cortex-A710 erratum 1901946 is a Cat B erratum that applies
to revision r1p0 and is fixed in r2p0.
The workaround is to set CPUACTLR4_EL1[15]. This has a slight
performance impact.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101
Change-Id: I703f0e6ee122e44a9bc284d90f1465039e3b40e4
Signed-off-by: John Powell <john.powell@arm.com>
show more ...
|