1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a710.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26.global check_erratum_cortex_a710_3701772 27 28#if WORKAROUND_CVE_2022_23960 29 wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 30#endif /* WORKAROUND_CVE_2022_23960 */ 31 32cpu_reset_prologue cortex_a710 33 34workaround_reset_start cortex_a710, ERRATUM(1901946), ERRATA_A710_1901946 35 sysreg_bit_set CORTEX_A710_CPUACTLR4_EL1, BIT(15) 36workaround_reset_end cortex_a710, ERRATUM(1901946) 37 38check_erratum_range cortex_a710, ERRATUM(1901946), CPU_REV(1, 0), CPU_REV(1, 0) 39 40workaround_reset_start cortex_a710, ERRATUM(1916945), ERRATA_A710_1916945 41 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(8) 42workaround_reset_end cortex_a710, ERRATUM(1916945) 43 44check_erratum_ls cortex_a710, ERRATUM(1916945), CPU_REV(1, 0) 45 46workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031 47 ldr x0,=0x6 48 msr S3_6_c15_c8_0,x0 49 ldr x0,=0xF3A08002 50 msr S3_6_c15_c8_2,x0 51 ldr x0,=0xFFF0F7FE 52 msr S3_6_c15_c8_3,x0 53 ldr x0,=0x40000001003ff 54 msr S3_6_c15_c8_1,x0 55 ldr x0,=0x7 56 msr S3_6_c15_c8_0,x0 57 ldr x0,=0xBF200000 58 msr S3_6_c15_c8_2,x0 59 ldr x0,=0xFFEF0000 60 msr S3_6_c15_c8_3,x0 61 ldr x0,=0x40000001003f3 62 msr S3_6_c15_c8_1,x0 63workaround_reset_end cortex_a710, ERRATUM(1987031) 64 65check_erratum_ls cortex_a710, ERRATUM(1987031), CPU_REV(2, 0) 66 67workaround_runtime_start cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768 68 /* Stash ERRSELR_EL1 in x2 */ 69 mrs x2, ERRSELR_EL1 70 71 /* Select error record 0 and clear ED bit */ 72 msr ERRSELR_EL1, xzr 73 mrs x1, ERXCTLR_EL1 74 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 75 msr ERXCTLR_EL1, x1 76 77 /* Select error record 1 and clear ED bit */ 78 mov x0, #1 79 msr ERRSELR_EL1, x0 80 mrs x1, ERXCTLR_EL1 81 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 82 msr ERXCTLR_EL1, x1 83 84 /* Restore ERRSELR_EL1 from x2 */ 85 msr ERRSELR_EL1, x2 86workaround_runtime_end cortex_a710, ERRATUM(2008768), NO_ISB 87 88check_erratum_ls cortex_a710, ERRATUM(2008768), CPU_REV(2, 0) 89 90workaround_reset_start cortex_a710, ERRATUM(2017096), ERRATA_A710_2017096 91 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT 92workaround_reset_end cortex_a710, ERRATUM(2017096) 93 94check_erratum_ls cortex_a710, ERRATUM(2017096), CPU_REV(2, 0) 95 96workaround_reset_start cortex_a710, ERRATUM(2055002), ERRATA_A710_2055002 97 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_46 98workaround_reset_end cortex_a710, ERRATUM(2055002) 99 100check_erratum_range cortex_a710, ERRATUM(2055002), CPU_REV(1, 0), CPU_REV(2, 0) 101 102workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180 103 ldr x0,=0x3 104 msr S3_6_c15_c8_0,x0 105 ldr x0,=0xF3A08002 106 msr S3_6_c15_c8_2,x0 107 ldr x0,=0xFFF0F7FE 108 msr S3_6_c15_c8_3,x0 109 ldr x0,=0x10002001003FF 110 msr S3_6_c15_c8_1,x0 111 ldr x0,=0x4 112 msr S3_6_c15_c8_0,x0 113 ldr x0,=0xBF200000 114 msr S3_6_c15_c8_2,x0 115 ldr x0,=0xFFEF0000 116 msr S3_6_c15_c8_3,x0 117 ldr x0,=0x10002001003F3 118 msr S3_6_c15_c8_1,x0 119workaround_reset_end cortex_a710, ERRATUM(2081180) 120 121check_erratum_ls cortex_a710, ERRATUM(2081180), CPU_REV(2, 0) 122 123workaround_reset_start cortex_a710, ERRATUM(2083908), ERRATA_A710_2083908 124 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 125workaround_reset_end cortex_a710, ERRATUM(2083908) 126 127check_erratum_range cortex_a710, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 128 129workaround_reset_start cortex_a710, ERRATUM(2136059), ERRATA_A710_2136059 130 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 131workaround_reset_end cortex_a710, ERRATUM(2136059) 132 133check_erratum_ls cortex_a710, ERRATUM(2136059), CPU_REV(2, 0) 134 135workaround_reset_start cortex_a710, ERRATUM(2147715), ERRATA_A710_2147715 136 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 137workaround_reset_end cortex_a710, ERRATUM(2147715) 138 139check_erratum_range cortex_a710, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 140 141workaround_reset_start cortex_a710, ERRATUM(2216384), ERRATA_A710_2216384 142 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_17 143 144 ldr x0,=0x5 145 msr CORTEX_A710_CPUPSELR_EL3, x0 146 ldr x0,=0x10F600E000 147 msr CORTEX_A710_CPUPOR_EL3, x0 148 ldr x0,=0x10FF80E000 149 msr CORTEX_A710_CPUPMR_EL3, x0 150 ldr x0,=0x80000000003FF 151 msr CORTEX_A710_CPUPCR_EL3, x0 152workaround_reset_end cortex_a710, ERRATUM(2216384) 153 154check_erratum_ls cortex_a710, ERRATUM(2216384), CPU_REV(2, 0) 155 156workaround_reset_start cortex_a710, ERRATUM(2267065), ERRATA_A710_2267065 157 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 158workaround_reset_end cortex_a710, ERRATUM(2267065) 159 160check_erratum_ls cortex_a710, ERRATUM(2267065), CPU_REV(2, 0) 161 162workaround_reset_start cortex_a710, ERRATUM(2282622), ERRATA_A710_2282622 163 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, BIT(0) 164workaround_reset_end cortex_a710, ERRATUM(2282622) 165 166check_erratum_ls cortex_a710, ERRATUM(2282622), CPU_REV(2, 1) 167 168.global erratum_cortex_a710_2291219_wa 169workaround_runtime_start cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219 170 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 171 * the workaround. Second call clears it to undo it. */ 172 sysreg_bit_toggle CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_36 173workaround_runtime_end cortex_a710, ERRATUM(2291219), NO_ISB 174 175check_erratum_ls cortex_a710, ERRATUM(2291219), CPU_REV(2, 0) 176 177workaround_reset_start cortex_a710, ERRATUM(2313941), ERRATA_DSU_2313941 178 errata_dsu_2313941_wa_impl 179workaround_reset_end cortex_a710, ERRATUM(2313941) 180 181check_erratum_custom_start cortex_a710, ERRATUM(2313941) 182 check_errata_dsu_2313941_impl 183 ret 184check_erratum_custom_end cortex_a710, ERRATUM(2313941) 185 186workaround_reset_start cortex_a710, ERRATUM(2371105), ERRATA_A710_2371105 187 /* Set bit 40 in CPUACTLR2_EL1 */ 188 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_40 189workaround_reset_end cortex_a710, ERRATUM(2371105) 190 191check_erratum_ls cortex_a710, ERRATUM(2371105), CPU_REV(2, 0) 192 193workaround_reset_start cortex_a710, ERRATUM(2742423), ERRATA_A710_2742423 194 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 195 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(55) 196 sysreg_bit_clear CORTEX_A710_CPUACTLR5_EL1, BIT(56) 197workaround_reset_end cortex_a710, ERRATUM(2742423) 198 199check_erratum_ls cortex_a710, ERRATUM(2742423), CPU_REV(2, 1) 200 201workaround_runtime_start cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515 202 /* dsb before isb of power down sequence */ 203 dsb sy 204workaround_runtime_end cortex_a710, ERRATUM(2768515), NO_ISB 205 206check_erratum_ls cortex_a710, ERRATUM(2768515), CPU_REV(2, 1) 207 208workaround_reset_start cortex_a710, ERRATUM(2778471), ERRATA_A710_2778471 209 sysreg_bit_set CORTEX_A710_CPUACTLR3_EL1, BIT(47) 210workaround_reset_end cortex_a710, ERRATUM(2778471) 211 212check_erratum_ls cortex_a710, ERRATUM(2778471), CPU_REV(2, 1) 213 214add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772 215 216check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1) 217 218workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 219#if IMAGE_BL31 220 /* 221 * The Cortex-A710 generic vectors are overridden to apply errata 222 * mitigation on exception entry from lower ELs. 223 */ 224 override_vector_table wa_cve_vbar_cortex_a710 225#endif /* IMAGE_BL31 */ 226workaround_reset_end cortex_a710, CVE(2022, 23960) 227 228check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 229 230/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 231workaround_reset_start cortex_a710, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 232 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(46) 233workaround_reset_end cortex_a710, CVE(2024, 5660) 234 235check_erratum_ls cortex_a710, CVE(2024, 5660), CPU_REV(2, 1) 236 237 /* ---------------------------------------------------- 238 * HW will do the cache maintenance while powering down 239 * ---------------------------------------------------- 240 */ 241func cortex_a710_core_pwr_dwn 242 apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768, NO_GET_CPU_REV 243 apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV 244 245 /* --------------------------------------------------- 246 * Enable CPU power down bit in power control register 247 * --------------------------------------------------- 248 */ 249 sysreg_bit_set CORTEX_A710_CPUPWRCTLR_EL1, CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 250 apply_erratum cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515, NO_GET_CPU_REV 251 isb 252 ret 253endfunc cortex_a710_core_pwr_dwn 254 255cpu_reset_func_start cortex_a710 256 /* Disable speculative loads */ 257 msr SSBS, xzr 258 enable_mpmm 259cpu_reset_func_end cortex_a710 260 261 /* --------------------------------------------- 262 * This function provides Cortex-A710 specific 263 * register information for crash reporting. 264 * It needs to return with x6 pointing to 265 * a list of register names in ascii and 266 * x8 - x15 having values of registers to be 267 * reported. 268 * --------------------------------------------- 269 */ 270.section .rodata.cortex_a710_regs, "aS" 271cortex_a710_regs: /* The ascii list of register names to be reported */ 272 .asciz "cpuectlr_el1", "" 273 274func cortex_a710_cpu_reg_dump 275 adr x6, cortex_a710_regs 276 mrs x8, CORTEX_A710_CPUECTLR_EL1 277 ret 278endfunc cortex_a710_cpu_reg_dump 279 280declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ 281 cortex_a710_reset_func, \ 282 cortex_a710_core_pwr_dwn 283