History log of /rk3399_ARM-atf/lib/el3_runtime/aarch64/context_mgmt.c (Results 126 – 150 of 361)
Revision Date Author Comments
# eee0ec48 26-Mar-2024 Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Merge changes from topic "mte_fixes" into integration

* changes:
build(changelog): move mte to mte2
refactor(mte): remove mte, mte_perm


# c282384d 07-Mar-2024 Govindraj Raja <govindraj.raja@arm.com>

refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently cont

refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently context saved/restored are needed
only when FEAT_MTE2 is enabled, so move to usage of FEAT_MTE2 and
remove FEAT_MTE usage.

BREAKING CHANGE: Any platform or downstream code trying to use
SCR_EL3.ATA bit(26) will see failures as this is now moved to be
used only with FEAT_MTE2 with
commit@ef0d0e5478a3f19cbe70a378b9b184036db38fe2

Change-Id: Id01e154156571f7792135639e17dc5c8d0e17cf8
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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# 869ee086 22-Mar-2024 Manish Pandey <manish.pandey2@arm.com>

Merge "fix(mte): use ATA bit with FEAT_MTE2" into integration


# ceedd1dc 22-Mar-2024 Manish Pandey <manish.pandey2@arm.com>

Merge "refactor(cm): minor update on conditions used in prepare_el3_exit" into integration


# d39b1236 06-Mar-2024 Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

refactor(cm): minor update on conditions used in prepare_el3_exit

This patch covers the following:

* Conditions set for verifying the EL2 presence and its usage
for various scenarios while exitin

refactor(cm): minor update on conditions used in prepare_el3_exit

This patch covers the following:

* Conditions set for verifying the EL2 presence and its usage
for various scenarios while exiting to Non secure world
"cm_prepare_el3_exit" has been improved.

* It thereby also fixes the issue(misra_c_2012_rule_15_7_violation)
for not terminating "if..else if" construct with an else statement
and keeps code in accordance with MISRA standards.

Change-Id: Ie5284447f5ac91412552629b76dbf2e636a09fd9
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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# ef0d0e54 28-Feb-2024 Govindraj Raja <govindraj.raja@arm.com>

fix(mte): use ATA bit with FEAT_MTE2

Currently SCR_EL3.ATA bit(26) is used freely or either with FEAT_MTE,
But ATA bit is available only with FEAT_MTE2. So use FEAT_MTE2
conditional check for use of

fix(mte): use ATA bit with FEAT_MTE2

Currently SCR_EL3.ATA bit(26) is used freely or either with FEAT_MTE,
But ATA bit is available only with FEAT_MTE2. So use FEAT_MTE2
conditional check for use of SCR_EL3.ATA.

Ref:
https://developer.arm.com/documentation/ddi0601/2023-12/AArch64-Registers/SCR-EL3--Secure-Configuration-Register?lang=en#fieldset_0-26_26-1

Change-Id: I0a5766a138b0be760c5584014f1ab817e4207a93
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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# e8090ce2 08-Mar-2024 Manish Pandey <manish.pandey2@arm.com>

Merge "refactor(cm): couple el2 registers with dependent feature flags" into integration


# d6af2344 24-Jan-2024 Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

refactor(cm): couple el2 registers with dependent feature flags

Currently the EL2 part of the context structure (el2_sysregs_t), is
mostly feature dependent.

For instance, CTX_HCRX_EL2 is only need

refactor(cm): couple el2 registers with dependent feature flags

Currently the EL2 part of the context structure (el2_sysregs_t), is
mostly feature dependent.

For instance, CTX_HCRX_EL2 is only needed when FEAT_HCX
(ENABLE_FEAT_HCX=1) is set, but the entry is unconditionally added
in the EL2 context structure and thereby consuming memory even in
build configurations where FEAT_HCX is disabled.

Henceforth, all such context entries should be coupled/tied with
their respective feature enables and be optimized away when unused.
This would reduce the context memory allocation for platforms, that
dont enable/support all the architectural features at once.

Further, converting the assembly context-offset entries into
a c structure relies on garbage collection of the linker
removing unreferenced structures from memory, as well as aiding
in readability and future maintenance.

Change-Id: I0cf49498ee3033cb6f3ee3810331121b26627783
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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# 885e93f9 22-Feb-2024 Olivier Deprez <olivier.deprez@arm.com>

Merge "fix(cm): update gic el2 sysregs save/restore mechanism" into integration


# 81f0f8c3 22-Feb-2024 Olivier Deprez <olivier.deprez@arm.com>

Merge changes from topic "jc/el1_ctx_optimization" into integration

* changes:
refactor(context-mgmt): remove el1_context routines from RMM
refactor(context-mgmt): move EL1 save/restore routines

Merge changes from topic "jc/el1_ctx_optimization" into integration

* changes:
refactor(context-mgmt): remove el1_context routines from RMM
refactor(context-mgmt): move EL1 save/restore routines into C

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# 59f8882b 08-Jan-2024 Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

refactor(context-mgmt): move EL1 save/restore routines into C

Similar to the refactoring process followed for EL2 system registers,
moving the save and restore routines of EL1 system registers into

refactor(context-mgmt): move EL1 save/restore routines into C

Similar to the refactoring process followed for EL2 system registers,
moving the save and restore routines of EL1 system registers into C
file, thereby reducing assembly code.

Change-Id: Ib59fbbe2eef2aa815effe854cf962fc4ac62a2ae
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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# 937d6fdb 05-Feb-2024 Manish Pandey <manish.pandey2@arm.com>

fix(cm): update gic el2 sysregs save/restore mechanism

This patch does following two changes
- Create a separate routine for saving/restoring GIC el2 system registers
- To access ICC_SRE_EL2 registe

fix(cm): update gic el2 sysregs save/restore mechanism

This patch does following two changes
- Create a separate routine for saving/restoring GIC el2 system registers
- To access ICC_SRE_EL2 register there was a workaround to set
SCR_EL3.NS before accessing it. This was required because SCR_EL3.EEL2
was zero. But with commit f105dd5fa this bit has been set to one early
on in booting process for a system with FEAT_SEL2 present and S-EL2
enabled.
However, we still need the workaround for a system which needs
save/restore of EL2 registers without secure EL2 being enabled e.g.
system with Non-secure and Realm world present.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I8d55c3dc6a17c4749748822d4a738912c1e13298

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# eb889865 12-Feb-2024 Olivier Deprez <olivier.deprez@arm.com>

Merge "feat(mte): add mte2 feat" into integration


# 8e397889 26-Jan-2024 Govindraj Raja <govindraj.raja@arm.com>

feat(mte): add mte2 feat

Add support for feat mte2. tfsr_el2 is available only with mte2,
however currently its context_save/restore is done with mte rather than
mte2, so introduce 'is_feat_mte2_sup

feat(mte): add mte2 feat

Add support for feat mte2. tfsr_el2 is available only with mte2,
however currently its context_save/restore is done with mte rather than
mte2, so introduce 'is_feat_mte2_supported' to check mte2.

Change-Id: I108d9989a8f5b4d1d2f3b9865a914056fa566cf2
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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# 7516d93d 29-Jan-2024 Manish Pandey <manish.pandey2@arm.com>

Merge "feat(cpufeat): add feature detection for FEAT_CSV2_3" into integration


# 30019d86 25-Oct-2023 Sona Mathew <sonarebecca.mathew@arm.com>

feat(cpufeat): add feature detection for FEAT_CSV2_3

This feature provides support to context save the
SCXTNUM_ELx register. FEAT_CSV2_3 implies the implementation
of FEAT_CSV2_2. FEAT_CSV2_3 is sup

feat(cpufeat): add feature detection for FEAT_CSV2_3

This feature provides support to context save the
SCXTNUM_ELx register. FEAT_CSV2_3 implies the implementation
of FEAT_CSV2_2. FEAT_CSV2_3 is supported in AArch64 state only
and is an optional feature in Arm v8.0 implementations.

This patch adds feature detection for v8.9 feature FEAT_CSV2_3,
adds macros for ID_AA64PFR0_EL1.CSV2 bits [59:56] for detecting
FEAT_CSV2_3 and macro for ENABLE_FEAT_CSV2_3.

Change-Id: Ida9f31e832b5f11bd89eebd6cc9f10ddad755c14
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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# 6c74b556 25-Jan-2024 Manish V Badarkhe <manish.badarkhe@arm.com>

Merge "fix(mte): remove CTX_INCLUDE_MTE_REGS usage" into integration


# 30788a84 25-Jan-2024 Govindraj Raja <govindraj.raja@arm.com>

fix(mte): remove CTX_INCLUDE_MTE_REGS usage

commit@0a33adc058080433f73bde73895266068990245c
Deprecated CTX_INCLUDE_MTE_REGS but missed its usage in
context save and restore path.

Change-Id: I30544a

fix(mte): remove CTX_INCLUDE_MTE_REGS usage

commit@0a33adc058080433f73bde73895266068990245c
Deprecated CTX_INCLUDE_MTE_REGS but missed its usage in
context save and restore path.

Change-Id: I30544abdff2cf92ff05d2d4df46ffc6ff10611de
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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# 61dfdfd4 24-Jan-2024 Manish V Badarkhe <manish.badarkhe@arm.com>

Merge "refactor(mte): deprecate CTX_INCLUDE_MTE_REGS" into integration


# 0a33adc0 21-Dec-2023 Govindraj Raja <govindraj.raja@arm.com>

refactor(mte): deprecate CTX_INCLUDE_MTE_REGS

Currently CTX_INCLUDE_MTE_REGS is used for dual purpose,
to enable allocation tags register and to context save and restore
them and also to check if mt

refactor(mte): deprecate CTX_INCLUDE_MTE_REGS

Currently CTX_INCLUDE_MTE_REGS is used for dual purpose,
to enable allocation tags register and to context save and restore
them and also to check if mte feature is available.

To make it more meaningful, remove CTX_INCLUDE_MTE_REGS
and introduce FEAT_MTE. This would enable allocation tags register
when FEAT_MTE is enabled and also supported from platform.

Also arch features can be conditionally enabled disabled based on
arch version from `make_helpers/arch_features.mk`

Change-Id: Ibdd2d43874634ad7ddff93c7edad6044ae1631ed
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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# e631ac3b 29-Dec-2023 Manish Pandey <manish.pandey2@arm.com>

Merge "build(mpam): add new build option CTX_INCLUDE_MPAM_REGS" into integration


# 9acff28a 06-Oct-2023 Arvind Ram Prakash <arvind.ramprakash@arm.com>

build(mpam): add new build option CTX_INCLUDE_MPAM_REGS

New build option CTX_INCLUDE_MPAM_REGS is added to select
if the firmware needs to save the MPAM EL2 registers during world
switches. This opt

build(mpam): add new build option CTX_INCLUDE_MPAM_REGS

New build option CTX_INCLUDE_MPAM_REGS is added to select
if the firmware needs to save the MPAM EL2 registers during world
switches. This option is currently disabled as MPAM is only
enabled for NS world.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ie2e5e184cdb65f7e1a98d8fe81590253fd859679

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# 11f99e8d 21-Dec-2023 Manish Pandey <manish.pandey2@arm.com>

Merge "refactor(cm): move MPAM3_EL3 reg to per world context" into integration


# ac4f6aaf 08-Nov-2023 Arvind Ram Prakash <arvind.ramprakash@arm.com>

refactor(cm): move MPAM3_EL3 reg to per world context

Refactor MPAM3_EL3 to be world-specific, eliminating redundant cross-CPU
value duplication and reducing memory footprint.

Signed-off-by: Arvind

refactor(cm): move MPAM3_EL3 reg to per world context

Refactor MPAM3_EL3 to be world-specific, eliminating redundant cross-CPU
value duplication and reducing memory footprint.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Iddf020a5462737e01ac35e4f2b2b204a8759fafb

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# 10636502 20-Dec-2023 Manish Pandey <manish.pandey2@arm.com>

Merge "refactor(cm): reset the cptr_el3 before perworld context setup" into integration


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