1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/cpu_data.h> 24 #include <lib/el3_runtime/pubsub_events.h> 25 #include <lib/extensions/amu.h> 26 #include <lib/extensions/brbe.h> 27 #include <lib/extensions/mpam.h> 28 #include <lib/extensions/pmuv3.h> 29 #include <lib/extensions/sme.h> 30 #include <lib/extensions/spe.h> 31 #include <lib/extensions/sve.h> 32 #include <lib/extensions/sys_reg_trace.h> 33 #include <lib/extensions/trbe.h> 34 #include <lib/extensions/trf.h> 35 #include <lib/utils.h> 36 37 #if ENABLE_FEAT_TWED 38 /* Make sure delay value fits within the range(0-15) */ 39 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 40 #endif /* ENABLE_FEAT_TWED */ 41 42 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 43 static bool has_secure_perworld_init; 44 45 static void manage_extensions_nonsecure(cpu_context_t *ctx); 46 static void manage_extensions_secure(cpu_context_t *ctx); 47 static void manage_extensions_secure_per_world(void); 48 49 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 50 { 51 u_register_t sctlr_elx, actlr_elx; 52 53 /* 54 * Initialise SCTLR_EL1 to the reset value corresponding to the target 55 * execution state setting all fields rather than relying on the hw. 56 * Some fields have architecturally UNKNOWN reset values and these are 57 * set to zero. 58 * 59 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 60 * 61 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 62 * required by PSCI specification) 63 */ 64 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 65 if (GET_RW(ep->spsr) == MODE_RW_64) { 66 sctlr_elx |= SCTLR_EL1_RES1; 67 } else { 68 /* 69 * If the target execution state is AArch32 then the following 70 * fields need to be set. 71 * 72 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 73 * instructions are not trapped to EL1. 74 * 75 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 76 * instructions are not trapped to EL1. 77 * 78 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 79 * CP15DMB, CP15DSB, and CP15ISB instructions. 80 */ 81 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 82 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 83 } 84 85 #if ERRATA_A75_764081 86 /* 87 * If workaround of errata 764081 for Cortex-A75 is used then set 88 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 89 */ 90 sctlr_elx |= SCTLR_IESB_BIT; 91 #endif 92 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 93 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 94 95 /* 96 * Base the context ACTLR_EL1 on the current value, as it is 97 * implementation defined. The context restore process will write 98 * the value from the context to the actual register and can cause 99 * problems for processor cores that don't expect certain bits to 100 * be zero. 101 */ 102 actlr_elx = read_actlr_el1(); 103 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 104 } 105 106 /****************************************************************************** 107 * This function performs initializations that are specific to SECURE state 108 * and updates the cpu context specified by 'ctx'. 109 *****************************************************************************/ 110 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 111 { 112 u_register_t scr_el3; 113 el3_state_t *state; 114 115 state = get_el3state_ctx(ctx); 116 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 117 118 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 119 /* 120 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 121 * indicated by the interrupt routing model for BL31. 122 */ 123 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 124 #endif 125 126 /* Allow access to Allocation Tags when mte is set*/ 127 if (is_feat_mte_supported()) { 128 scr_el3 |= SCR_ATA_BIT; 129 } 130 131 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 132 133 /* 134 * Initialize EL1 context registers unless SPMC is running 135 * at S-EL2. 136 */ 137 #if !SPMD_SPM_AT_SEL2 138 setup_el1_context(ctx, ep); 139 #endif 140 141 manage_extensions_secure(ctx); 142 143 /** 144 * manage_extensions_secure_per_world api has to be executed once, 145 * as the registers getting initialised, maintain constant value across 146 * all the cpus for the secure world. 147 * Henceforth, this check ensures that the registers are initialised once 148 * and avoids re-initialization from multiple cores. 149 */ 150 if (!has_secure_perworld_init) { 151 manage_extensions_secure_per_world(); 152 } 153 154 } 155 156 #if ENABLE_RME 157 /****************************************************************************** 158 * This function performs initializations that are specific to REALM state 159 * and updates the cpu context specified by 'ctx'. 160 *****************************************************************************/ 161 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 162 { 163 u_register_t scr_el3; 164 el3_state_t *state; 165 166 state = get_el3state_ctx(ctx); 167 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 168 169 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 170 171 /* CSV2 version 2 and above */ 172 if (is_feat_csv2_2_supported()) { 173 /* Enable access to the SCXTNUM_ELx registers. */ 174 scr_el3 |= SCR_EnSCXT_BIT; 175 } 176 177 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 178 } 179 #endif /* ENABLE_RME */ 180 181 /****************************************************************************** 182 * This function performs initializations that are specific to NON-SECURE state 183 * and updates the cpu context specified by 'ctx'. 184 *****************************************************************************/ 185 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 186 { 187 u_register_t scr_el3; 188 el3_state_t *state; 189 190 state = get_el3state_ctx(ctx); 191 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 192 193 /* SCR_NS: Set the NS bit */ 194 scr_el3 |= SCR_NS_BIT; 195 196 /* Allow access to Allocation Tags when MTE is implemented. */ 197 scr_el3 |= SCR_ATA_BIT; 198 199 #if !CTX_INCLUDE_PAUTH_REGS 200 /* 201 * Pointer Authentication feature, if present, is always enabled by default 202 * for Non secure lower exception levels. We do not have an explicit 203 * flag to set it. 204 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 205 * exception levels of secure and realm worlds. 206 * 207 * To prevent the leakage between the worlds during world switch, 208 * we enable it only for the non-secure world. 209 * 210 * If the Secure/realm world wants to use pointer authentication, 211 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 212 * it will be enabled globally for all the contexts. 213 * 214 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 215 * other than EL3 216 * 217 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 218 * than EL3 219 */ 220 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 221 222 #endif /* CTX_INCLUDE_PAUTH_REGS */ 223 224 #if HANDLE_EA_EL3_FIRST_NS 225 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 226 scr_el3 |= SCR_EA_BIT; 227 #endif 228 229 #if RAS_TRAP_NS_ERR_REC_ACCESS 230 /* 231 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 232 * and RAS ERX registers from EL1 and EL2(from any security state) 233 * are trapped to EL3. 234 * Set here to trap only for NS EL1/EL2 235 * 236 */ 237 scr_el3 |= SCR_TERR_BIT; 238 #endif 239 240 /* CSV2 version 2 and above */ 241 if (is_feat_csv2_2_supported()) { 242 /* Enable access to the SCXTNUM_ELx registers. */ 243 scr_el3 |= SCR_EnSCXT_BIT; 244 } 245 246 #ifdef IMAGE_BL31 247 /* 248 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 249 * indicated by the interrupt routing model for BL31. 250 */ 251 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 252 #endif 253 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 254 255 /* Initialize EL1 context registers */ 256 setup_el1_context(ctx, ep); 257 258 /* Initialize EL2 context registers */ 259 #if CTX_INCLUDE_EL2_REGS 260 261 /* 262 * Initialize SCTLR_EL2 context register using Endianness value 263 * taken from the entrypoint attribute. 264 */ 265 u_register_t sctlr_el2_val = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 266 sctlr_el2_val |= SCTLR_EL2_RES1; 267 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, sctlr_el2_val); 268 269 270 if (is_feat_hcx_supported()) { 271 /* 272 * Initialize register HCRX_EL2 with its init value. 273 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 274 * chance that this can lead to unexpected behavior in lower 275 * ELs that have not been updated since the introduction of 276 * this feature if not properly initialized, especially when 277 * it comes to those bits that enable/disable traps. 278 */ 279 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 280 HCRX_EL2_INIT_VAL); 281 } 282 283 if (is_feat_fgt_supported()) { 284 /* 285 * Initialize HFG*_EL2 registers with a default value so legacy 286 * systems unaware of FEAT_FGT do not get trapped due to their lack 287 * of initialization for this feature. 288 */ 289 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 290 HFGITR_EL2_INIT_VAL); 291 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 292 HFGRTR_EL2_INIT_VAL); 293 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 294 HFGWTR_EL2_INIT_VAL); 295 } 296 297 #endif /* CTX_INCLUDE_EL2_REGS */ 298 299 manage_extensions_nonsecure(ctx); 300 } 301 302 /******************************************************************************* 303 * The following function performs initialization of the cpu_context 'ctx' 304 * for first use that is common to all security states, and sets the 305 * initial entrypoint state as specified by the entry_point_info structure. 306 * 307 * The EE and ST attributes are used to configure the endianness and secure 308 * timer availability for the new execution context. 309 ******************************************************************************/ 310 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 311 { 312 u_register_t scr_el3; 313 el3_state_t *state; 314 gp_regs_t *gp_regs; 315 316 state = get_el3state_ctx(ctx); 317 318 /* Clear any residual register values from the context */ 319 zeromem(ctx, sizeof(*ctx)); 320 321 /* 322 * The lower-EL context is zeroed so that no stale values leak to a world. 323 * It is assumed that an all-zero lower-EL context is good enough for it 324 * to boot correctly. However, there are very few registers where this 325 * is not true and some values need to be recreated. 326 */ 327 #if CTX_INCLUDE_EL2_REGS 328 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 329 330 /* 331 * These bits are set in the gicv3 driver. Losing them (especially the 332 * SRE bit) is problematic for all worlds. Henceforth recreate them. 333 */ 334 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 335 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 336 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 337 #endif /* CTX_INCLUDE_EL2_REGS */ 338 339 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 340 scr_el3 = SCR_RESET_VAL; 341 342 /* 343 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 344 * EL2, EL1 and EL0 are not trapped to EL3. 345 * 346 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 347 * EL2, EL1 and EL0 are not trapped to EL3. 348 * 349 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 350 * both Security states and both Execution states. 351 * 352 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 353 * Non-secure memory. 354 */ 355 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 356 357 scr_el3 |= SCR_SIF_BIT; 358 359 /* 360 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 361 * Exception level as specified by SPSR. 362 */ 363 if (GET_RW(ep->spsr) == MODE_RW_64) { 364 scr_el3 |= SCR_RW_BIT; 365 } 366 367 /* 368 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 369 * Secure timer registers to EL3, from AArch64 state only, if specified 370 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 371 * bit always behaves as 1 (i.e. secure physical timer register access 372 * is not trapped) 373 */ 374 if (EP_GET_ST(ep->h.attr) != 0U) { 375 scr_el3 |= SCR_ST_BIT; 376 } 377 378 /* 379 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 380 * SCR_EL3.HXEn. 381 */ 382 if (is_feat_hcx_supported()) { 383 scr_el3 |= SCR_HXEn_BIT; 384 } 385 386 /* 387 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 388 * registers are trapped to EL3. 389 */ 390 #if ENABLE_FEAT_RNG_TRAP 391 scr_el3 |= SCR_TRNDR_BIT; 392 #endif 393 394 #if FAULT_INJECTION_SUPPORT 395 /* Enable fault injection from lower ELs */ 396 scr_el3 |= SCR_FIEN_BIT; 397 #endif 398 399 #if CTX_INCLUDE_PAUTH_REGS 400 /* 401 * Enable Pointer Authentication globally for all the worlds. 402 * 403 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 404 * other than EL3 405 * 406 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 407 * than EL3 408 */ 409 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 410 #endif /* CTX_INCLUDE_PAUTH_REGS */ 411 412 /* 413 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 414 */ 415 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 416 scr_el3 |= SCR_TCR2EN_BIT; 417 } 418 419 /* 420 * SCR_EL3.PIEN: Enable permission indirection and overlay 421 * registers for AArch64 if present. 422 */ 423 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 424 scr_el3 |= SCR_PIEN_BIT; 425 } 426 427 /* 428 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 429 */ 430 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 431 scr_el3 |= SCR_GCSEn_BIT; 432 } 433 434 /* 435 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 436 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 437 * next mode is Hyp. 438 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 439 * same conditions as HVC instructions and when the processor supports 440 * ARMv8.6-FGT. 441 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 442 * CNTPOFF_EL2 register under the same conditions as HVC instructions 443 * and when the processor supports ECV. 444 */ 445 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 446 || ((GET_RW(ep->spsr) != MODE_RW_64) 447 && (GET_M32(ep->spsr) == MODE32_hyp))) { 448 scr_el3 |= SCR_HCE_BIT; 449 450 if (is_feat_fgt_supported()) { 451 scr_el3 |= SCR_FGTEN_BIT; 452 } 453 454 if (is_feat_ecv_supported()) { 455 scr_el3 |= SCR_ECVEN_BIT; 456 } 457 } 458 459 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 460 if (is_feat_twed_supported()) { 461 /* Set delay in SCR_EL3 */ 462 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 463 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 464 << SCR_TWEDEL_SHIFT); 465 466 /* Enable WFE delay */ 467 scr_el3 |= SCR_TWEDEn_BIT; 468 } 469 470 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 471 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 472 if (is_feat_sel2_supported()) { 473 scr_el3 |= SCR_EEL2_BIT; 474 } 475 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 476 477 /* 478 * Populate EL3 state so that we've the right context 479 * before doing ERET 480 */ 481 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 482 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 483 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 484 485 /* 486 * Store the X0-X7 value from the entrypoint into the context 487 * Use memcpy as we are in control of the layout of the structures 488 */ 489 gp_regs = get_gpregs_ctx(ctx); 490 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 491 } 492 493 /******************************************************************************* 494 * Context management library initialization routine. This library is used by 495 * runtime services to share pointers to 'cpu_context' structures for secure 496 * non-secure and realm states. Management of the structures and their associated 497 * memory is not done by the context management library e.g. the PSCI service 498 * manages the cpu context used for entry from and exit to the non-secure state. 499 * The Secure payload dispatcher service manages the context(s) corresponding to 500 * the secure state. It also uses this library to get access to the non-secure 501 * state cpu context pointers. 502 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 503 * which will be used for programming an entry into a lower EL. The same context 504 * will be used to save state upon exception entry from that EL. 505 ******************************************************************************/ 506 void __init cm_init(void) 507 { 508 /* 509 * The context management library has only global data to initialize, but 510 * that will be done when the BSS is zeroed out. 511 */ 512 } 513 514 /******************************************************************************* 515 * This is the high-level function used to initialize the cpu_context 'ctx' for 516 * first use. It performs initializations that are common to all security states 517 * and initializations specific to the security state specified in 'ep' 518 ******************************************************************************/ 519 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 520 { 521 unsigned int security_state; 522 523 assert(ctx != NULL); 524 525 /* 526 * Perform initializations that are common 527 * to all security states 528 */ 529 setup_context_common(ctx, ep); 530 531 security_state = GET_SECURITY_STATE(ep->h.attr); 532 533 /* Perform security state specific initializations */ 534 switch (security_state) { 535 case SECURE: 536 setup_secure_context(ctx, ep); 537 break; 538 #if ENABLE_RME 539 case REALM: 540 setup_realm_context(ctx, ep); 541 break; 542 #endif 543 case NON_SECURE: 544 setup_ns_context(ctx, ep); 545 break; 546 default: 547 ERROR("Invalid security state\n"); 548 panic(); 549 break; 550 } 551 } 552 553 /******************************************************************************* 554 * Enable architecture extensions for EL3 execution. This function only updates 555 * registers in-place which are expected to either never change or be 556 * overwritten by el3_exit. 557 ******************************************************************************/ 558 #if IMAGE_BL31 559 void cm_manage_extensions_el3(void) 560 { 561 if (is_feat_spe_supported()) { 562 spe_init_el3(); 563 } 564 565 if (is_feat_amu_supported()) { 566 amu_init_el3(); 567 } 568 569 if (is_feat_sme_supported()) { 570 sme_init_el3(); 571 } 572 573 if (is_feat_trbe_supported()) { 574 trbe_init_el3(); 575 } 576 577 if (is_feat_brbe_supported()) { 578 brbe_init_el3(); 579 } 580 581 if (is_feat_trf_supported()) { 582 trf_init_el3(); 583 } 584 585 pmuv3_init_el3(); 586 } 587 #endif /* IMAGE_BL31 */ 588 589 /****************************************************************************** 590 * Function to initialise the registers with the RESET values in the context 591 * memory, which are maintained per world. 592 ******************************************************************************/ 593 #if IMAGE_BL31 594 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 595 { 596 /* 597 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 598 * 599 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 600 * by Advanced SIMD, floating-point or SVE instructions (if 601 * implemented) do not trap to EL3. 602 * 603 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 604 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 605 */ 606 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 607 608 per_world_ctx->ctx_cptr_el3 = cptr_el3; 609 610 /* 611 * Initialize MPAM3_EL3 to its default reset value 612 * 613 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 614 * all lower ELn MPAM3_EL3 register access to, trap to EL3 615 */ 616 617 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 618 } 619 #endif /* IMAGE_BL31 */ 620 621 /******************************************************************************* 622 * Initialise per_world_context for Non-Secure world. 623 * This function enables the architecture extensions, which have same value 624 * across the cores for the non-secure world. 625 ******************************************************************************/ 626 #if IMAGE_BL31 627 void manage_extensions_nonsecure_per_world(void) 628 { 629 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 630 631 if (is_feat_sme_supported()) { 632 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 633 } 634 635 if (is_feat_sve_supported()) { 636 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 637 } 638 639 if (is_feat_amu_supported()) { 640 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 641 } 642 643 if (is_feat_sys_reg_trace_supported()) { 644 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 645 } 646 647 if (is_feat_mpam_supported()) { 648 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 649 } 650 } 651 #endif /* IMAGE_BL31 */ 652 653 /******************************************************************************* 654 * Initialise per_world_context for Secure world. 655 * This function enables the architecture extensions, which have same value 656 * across the cores for the secure world. 657 ******************************************************************************/ 658 static void manage_extensions_secure_per_world(void) 659 { 660 #if IMAGE_BL31 661 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 662 663 if (is_feat_sme_supported()) { 664 665 if (ENABLE_SME_FOR_SWD) { 666 /* 667 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 668 * SME, SVE, and FPU/SIMD context properly managed. 669 */ 670 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 671 } else { 672 /* 673 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 674 * world can safely use the associated registers. 675 */ 676 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 677 } 678 } 679 if (is_feat_sve_supported()) { 680 if (ENABLE_SVE_FOR_SWD) { 681 /* 682 * Enable SVE and FPU in secure context, SPM must ensure 683 * that the SVE and FPU register contexts are properly managed. 684 */ 685 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 686 } else { 687 /* 688 * Disable SVE and FPU in secure context so non-secure world 689 * can safely use them. 690 */ 691 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 692 } 693 } 694 695 /* NS can access this but Secure shouldn't */ 696 if (is_feat_sys_reg_trace_supported()) { 697 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 698 } 699 700 has_secure_perworld_init = true; 701 #endif /* IMAGE_BL31 */ 702 } 703 704 /******************************************************************************* 705 * Enable architecture extensions on first entry to Non-secure world. 706 ******************************************************************************/ 707 static void manage_extensions_nonsecure(cpu_context_t *ctx) 708 { 709 #if IMAGE_BL31 710 if (is_feat_amu_supported()) { 711 amu_enable(ctx); 712 } 713 714 if (is_feat_sme_supported()) { 715 sme_enable(ctx); 716 } 717 718 pmuv3_enable(ctx); 719 #endif /* IMAGE_BL31 */ 720 } 721 722 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 723 static __unused void enable_pauth_el2(void) 724 { 725 u_register_t hcr_el2 = read_hcr_el2(); 726 /* 727 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 728 * accessing key registers or using pointer authentication instructions 729 * from lower ELs. 730 */ 731 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 732 733 write_hcr_el2(hcr_el2); 734 } 735 736 #if INIT_UNUSED_NS_EL2 737 /******************************************************************************* 738 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 739 * world when EL2 is empty and unused. 740 ******************************************************************************/ 741 static void manage_extensions_nonsecure_el2_unused(void) 742 { 743 #if IMAGE_BL31 744 if (is_feat_spe_supported()) { 745 spe_init_el2_unused(); 746 } 747 748 if (is_feat_amu_supported()) { 749 amu_init_el2_unused(); 750 } 751 752 if (is_feat_mpam_supported()) { 753 mpam_init_el2_unused(); 754 } 755 756 if (is_feat_trbe_supported()) { 757 trbe_init_el2_unused(); 758 } 759 760 if (is_feat_sys_reg_trace_supported()) { 761 sys_reg_trace_init_el2_unused(); 762 } 763 764 if (is_feat_trf_supported()) { 765 trf_init_el2_unused(); 766 } 767 768 pmuv3_init_el2_unused(); 769 770 if (is_feat_sve_supported()) { 771 sve_init_el2_unused(); 772 } 773 774 if (is_feat_sme_supported()) { 775 sme_init_el2_unused(); 776 } 777 778 #if ENABLE_PAUTH 779 enable_pauth_el2(); 780 #endif /* ENABLE_PAUTH */ 781 #endif /* IMAGE_BL31 */ 782 } 783 #endif /* INIT_UNUSED_NS_EL2 */ 784 785 /******************************************************************************* 786 * Enable architecture extensions on first entry to Secure world. 787 ******************************************************************************/ 788 static void manage_extensions_secure(cpu_context_t *ctx) 789 { 790 #if IMAGE_BL31 791 if (is_feat_sme_supported()) { 792 if (ENABLE_SME_FOR_SWD) { 793 /* 794 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 795 * must ensure SME, SVE, and FPU/SIMD context properly managed. 796 */ 797 sme_init_el3(); 798 sme_enable(ctx); 799 } else { 800 /* 801 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 802 * world can safely use the associated registers. 803 */ 804 sme_disable(ctx); 805 } 806 } 807 #endif /* IMAGE_BL31 */ 808 } 809 810 /******************************************************************************* 811 * The following function initializes the cpu_context for a CPU specified by 812 * its `cpu_idx` for first use, and sets the initial entrypoint state as 813 * specified by the entry_point_info structure. 814 ******************************************************************************/ 815 void cm_init_context_by_index(unsigned int cpu_idx, 816 const entry_point_info_t *ep) 817 { 818 cpu_context_t *ctx; 819 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 820 cm_setup_context(ctx, ep); 821 } 822 823 /******************************************************************************* 824 * The following function initializes the cpu_context for the current CPU 825 * for first use, and sets the initial entrypoint state as specified by the 826 * entry_point_info structure. 827 ******************************************************************************/ 828 void cm_init_my_context(const entry_point_info_t *ep) 829 { 830 cpu_context_t *ctx; 831 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 832 cm_setup_context(ctx, ep); 833 } 834 835 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 836 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 837 { 838 #if INIT_UNUSED_NS_EL2 839 u_register_t hcr_el2 = HCR_RESET_VAL; 840 u_register_t mdcr_el2; 841 u_register_t scr_el3; 842 843 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 844 845 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 846 if ((scr_el3 & SCR_RW_BIT) != 0U) { 847 hcr_el2 |= HCR_RW_BIT; 848 } 849 850 write_hcr_el2(hcr_el2); 851 852 /* 853 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 854 * All fields have architecturally UNKNOWN reset values. 855 */ 856 write_cptr_el2(CPTR_EL2_RESET_VAL); 857 858 /* 859 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 860 * reset and are set to zero except for field(s) listed below. 861 * 862 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 863 * Non-secure EL0 and EL1 accesses to the physical timer registers. 864 * 865 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 866 * Non-secure EL0 and EL1 accesses to the physical counter registers. 867 */ 868 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 869 870 /* 871 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 872 * UNKNOWN value. 873 */ 874 write_cntvoff_el2(0); 875 876 /* 877 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 878 * respectively. 879 */ 880 write_vpidr_el2(read_midr_el1()); 881 write_vmpidr_el2(read_mpidr_el1()); 882 883 /* 884 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 885 * 886 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 887 * translation is disabled, cache maintenance operations depend on the 888 * VMID. 889 * 890 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 891 * disabled. 892 */ 893 write_vttbr_el2(VTTBR_RESET_VAL & 894 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 895 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 896 897 /* 898 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 899 * Some fields are architecturally UNKNOWN on reset. 900 * 901 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 902 * register accesses to the Debug ROM registers are not trapped to EL2. 903 * 904 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 905 * accesses to the powerdown debug registers are not trapped to EL2. 906 * 907 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 908 * debug registers do not trap to EL2. 909 * 910 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 911 * EL2. 912 */ 913 mdcr_el2 = MDCR_EL2_RESET_VAL & 914 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 915 MDCR_EL2_TDE_BIT); 916 917 write_mdcr_el2(mdcr_el2); 918 919 /* 920 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 921 * 922 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 923 * EL1 accesses to System registers do not trap to EL2. 924 */ 925 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 926 927 /* 928 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 929 * reset. 930 * 931 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 932 * and prevent timer interrupts. 933 */ 934 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 935 936 manage_extensions_nonsecure_el2_unused(); 937 #endif /* INIT_UNUSED_NS_EL2 */ 938 } 939 940 /******************************************************************************* 941 * Prepare the CPU system registers for first entry into realm, secure, or 942 * normal world. 943 * 944 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 945 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 946 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 947 * For all entries, the EL1 registers are initialized from the cpu_context 948 ******************************************************************************/ 949 void cm_prepare_el3_exit(uint32_t security_state) 950 { 951 u_register_t sctlr_elx, scr_el3; 952 cpu_context_t *ctx = cm_get_context(security_state); 953 954 assert(ctx != NULL); 955 956 if (security_state == NON_SECURE) { 957 uint64_t el2_implemented = el_implemented(2); 958 959 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 960 CTX_SCR_EL3); 961 962 if (el2_implemented != EL_IMPL_NONE) { 963 964 /* 965 * If context is not being used for EL2, initialize 966 * HCRX_EL2 with its init value here. 967 */ 968 if (is_feat_hcx_supported()) { 969 write_hcrx_el2(HCRX_EL2_INIT_VAL); 970 } 971 972 /* 973 * Initialize Fine-grained trap registers introduced 974 * by FEAT_FGT so all traps are initially disabled when 975 * switching to EL2 or a lower EL, preventing undesired 976 * behavior. 977 */ 978 if (is_feat_fgt_supported()) { 979 /* 980 * Initialize HFG*_EL2 registers with a default 981 * value so legacy systems unaware of FEAT_FGT 982 * do not get trapped due to their lack of 983 * initialization for this feature. 984 */ 985 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 986 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 987 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 988 } 989 990 /* Condition to ensure EL2 is being used. */ 991 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 992 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 993 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 994 CTX_SCTLR_EL1); 995 sctlr_elx &= SCTLR_EE_BIT; 996 sctlr_elx |= SCTLR_EL2_RES1; 997 #if ERRATA_A75_764081 998 /* 999 * If workaround of errata 764081 for Cortex-A75 1000 * is used then set SCTLR_EL2.IESB to enable 1001 * Implicit Error Synchronization Barrier. 1002 */ 1003 sctlr_elx |= SCTLR_IESB_BIT; 1004 #endif /* ERRATA_A75_764081 */ 1005 write_sctlr_el2(sctlr_elx); 1006 } else { 1007 /* 1008 * (scr_el3 & SCR_HCE_BIT==0) 1009 * EL2 implemented but unused. 1010 */ 1011 init_nonsecure_el2_unused(ctx); 1012 } 1013 } 1014 } 1015 cm_el1_sysregs_context_restore(security_state); 1016 cm_set_next_eret_context(security_state); 1017 } 1018 1019 #if CTX_INCLUDE_EL2_REGS 1020 1021 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1022 { 1023 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1024 if (is_feat_amu_supported()) { 1025 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1026 } 1027 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1028 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1029 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1030 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1031 } 1032 1033 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1034 { 1035 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1036 if (is_feat_amu_supported()) { 1037 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1038 } 1039 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1040 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1041 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1042 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1043 } 1044 1045 #if CTX_INCLUDE_MPAM_REGS 1046 1047 static void el2_sysregs_context_save_mpam(mpam_t *ctx) 1048 { 1049 u_register_t mpam_idr = read_mpamidr_el1(); 1050 1051 write_ctx_reg(ctx, CTX_MPAM2_EL2, read_mpam2_el2()); 1052 1053 /* 1054 * The context registers that we intend to save would be part of the 1055 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1056 */ 1057 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1058 return; 1059 } 1060 1061 /* 1062 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1063 * MPAMIDR_HAS_HCR_BIT == 1. 1064 */ 1065 write_ctx_reg(ctx, CTX_MPAMHCR_EL2, read_mpamhcr_el2()); 1066 write_ctx_reg(ctx, CTX_MPAMVPM0_EL2, read_mpamvpm0_el2()); 1067 write_ctx_reg(ctx, CTX_MPAMVPMV_EL2, read_mpamvpmv_el2()); 1068 1069 /* 1070 * The number of MPAMVPM registers is implementation defined, their 1071 * number is stored in the MPAMIDR_EL1 register. 1072 */ 1073 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1074 case 7: 1075 write_ctx_reg(ctx, CTX_MPAMVPM7_EL2, read_mpamvpm7_el2()); 1076 __fallthrough; 1077 case 6: 1078 write_ctx_reg(ctx, CTX_MPAMVPM6_EL2, read_mpamvpm6_el2()); 1079 __fallthrough; 1080 case 5: 1081 write_ctx_reg(ctx, CTX_MPAMVPM5_EL2, read_mpamvpm5_el2()); 1082 __fallthrough; 1083 case 4: 1084 write_ctx_reg(ctx, CTX_MPAMVPM4_EL2, read_mpamvpm4_el2()); 1085 __fallthrough; 1086 case 3: 1087 write_ctx_reg(ctx, CTX_MPAMVPM3_EL2, read_mpamvpm3_el2()); 1088 __fallthrough; 1089 case 2: 1090 write_ctx_reg(ctx, CTX_MPAMVPM2_EL2, read_mpamvpm2_el2()); 1091 __fallthrough; 1092 case 1: 1093 write_ctx_reg(ctx, CTX_MPAMVPM1_EL2, read_mpamvpm1_el2()); 1094 break; 1095 } 1096 } 1097 1098 #endif /* CTX_INCLUDE_MPAM_REGS */ 1099 1100 #if CTX_INCLUDE_MPAM_REGS 1101 static void el2_sysregs_context_restore_mpam(mpam_t *ctx) 1102 { 1103 u_register_t mpam_idr = read_mpamidr_el1(); 1104 1105 write_mpam2_el2(read_ctx_reg(ctx, CTX_MPAM2_EL2)); 1106 1107 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1108 return; 1109 } 1110 1111 write_mpamhcr_el2(read_ctx_reg(ctx, CTX_MPAMHCR_EL2)); 1112 write_mpamvpm0_el2(read_ctx_reg(ctx, CTX_MPAMVPM0_EL2)); 1113 write_mpamvpmv_el2(read_ctx_reg(ctx, CTX_MPAMVPMV_EL2)); 1114 1115 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1116 case 7: 1117 write_mpamvpm7_el2(read_ctx_reg(ctx, CTX_MPAMVPM7_EL2)); 1118 __fallthrough; 1119 case 6: 1120 write_mpamvpm6_el2(read_ctx_reg(ctx, CTX_MPAMVPM6_EL2)); 1121 __fallthrough; 1122 case 5: 1123 write_mpamvpm5_el2(read_ctx_reg(ctx, CTX_MPAMVPM5_EL2)); 1124 __fallthrough; 1125 case 4: 1126 write_mpamvpm4_el2(read_ctx_reg(ctx, CTX_MPAMVPM4_EL2)); 1127 __fallthrough; 1128 case 3: 1129 write_mpamvpm3_el2(read_ctx_reg(ctx, CTX_MPAMVPM3_EL2)); 1130 __fallthrough; 1131 case 2: 1132 write_mpamvpm2_el2(read_ctx_reg(ctx, CTX_MPAMVPM2_EL2)); 1133 __fallthrough; 1134 case 1: 1135 write_mpamvpm1_el2(read_ctx_reg(ctx, CTX_MPAMVPM1_EL2)); 1136 break; 1137 } 1138 } 1139 #endif /* CTX_INCLUDE_MPAM_REGS */ 1140 1141 /* --------------------------------------------------------------------------- 1142 * The following registers are not added: 1143 * ICH_AP0R<n>_EL2 1144 * ICH_AP1R<n>_EL2 1145 * ICH_LR<n>_EL2 1146 * 1147 * NOTE: For a system with S-EL2 present but not enabled, accessing 1148 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1149 * SCR_EL3.NS = 1 before accessing this register. 1150 * --------------------------------------------------------------------------- 1151 */ 1152 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx) 1153 { 1154 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1155 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1156 #else 1157 u_register_t scr_el3 = read_scr_el3(); 1158 write_scr_el3(scr_el3 | SCR_NS_BIT); 1159 isb(); 1160 1161 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1162 1163 write_scr_el3(scr_el3); 1164 isb(); 1165 #endif 1166 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1167 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1168 } 1169 1170 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx) 1171 { 1172 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1173 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1174 #else 1175 u_register_t scr_el3 = read_scr_el3(); 1176 write_scr_el3(scr_el3 | SCR_NS_BIT); 1177 isb(); 1178 1179 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1180 1181 write_scr_el3(scr_el3); 1182 isb(); 1183 #endif 1184 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1185 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1186 } 1187 1188 /* ----------------------------------------------------- 1189 * The following registers are not added: 1190 * AMEVCNTVOFF0<n>_EL2 1191 * AMEVCNTVOFF1<n>_EL2 1192 * ----------------------------------------------------- 1193 */ 1194 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1195 { 1196 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1197 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1198 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1199 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1200 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1201 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1202 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1203 if (CTX_INCLUDE_AARCH32_REGS) { 1204 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1205 } 1206 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1207 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1208 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1209 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1210 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1211 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1212 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1213 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1214 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1215 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1216 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1217 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1218 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1219 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1220 write_el2_ctx_common(ctx, ttbr0_el2, read_ttbr0_el2()); 1221 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1222 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1223 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1224 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1225 write_el2_ctx_common(ctx, vttbr_el2, read_vttbr_el2()); 1226 } 1227 1228 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1229 { 1230 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1231 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1232 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1233 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1234 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1235 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1236 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1237 if (CTX_INCLUDE_AARCH32_REGS) { 1238 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1239 } 1240 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1241 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1242 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1243 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1244 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1245 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1246 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1247 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1248 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1249 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1250 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1251 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1252 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1253 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1254 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1255 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1256 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1257 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1258 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1259 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1260 } 1261 1262 /******************************************************************************* 1263 * Save EL2 sysreg context 1264 ******************************************************************************/ 1265 void cm_el2_sysregs_context_save(uint32_t security_state) 1266 { 1267 cpu_context_t *ctx; 1268 el2_sysregs_t *el2_sysregs_ctx; 1269 1270 ctx = cm_get_context(security_state); 1271 assert(ctx != NULL); 1272 1273 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1274 1275 el2_sysregs_context_save_common(el2_sysregs_ctx); 1276 el2_sysregs_context_save_gic(el2_sysregs_ctx); 1277 1278 if (is_feat_mte_supported()) { 1279 write_el2_ctx_mte(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1280 } 1281 1282 #if CTX_INCLUDE_MPAM_REGS 1283 if (is_feat_mpam_supported()) { 1284 mpam_t *mpam_ctx = get_mpam_ctx(ctx); 1285 el2_sysregs_context_save_mpam(mpam_ctx); 1286 } 1287 #endif 1288 1289 if (is_feat_fgt_supported()) { 1290 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1291 } 1292 1293 if (is_feat_ecv_v2_supported()) { 1294 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1295 } 1296 1297 if (is_feat_vhe_supported()) { 1298 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1299 read_contextidr_el2()); 1300 write_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1301 } 1302 1303 if (is_feat_ras_supported()) { 1304 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1305 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1306 } 1307 1308 if (is_feat_nv2_supported()) { 1309 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1310 } 1311 1312 if (is_feat_trf_supported()) { 1313 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1314 } 1315 1316 if (is_feat_csv2_2_supported()) { 1317 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1318 read_scxtnum_el2()); 1319 } 1320 1321 if (is_feat_hcx_supported()) { 1322 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1323 } 1324 1325 if (is_feat_tcr2_supported()) { 1326 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1327 } 1328 1329 if (is_feat_sxpie_supported()) { 1330 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1331 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1332 } 1333 1334 if (is_feat_sxpoe_supported()) { 1335 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1336 } 1337 1338 if (is_feat_s2pie_supported()) { 1339 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1340 } 1341 1342 if (is_feat_gcs_supported()) { 1343 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcspr_el2()); 1344 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcscr_el2()); 1345 } 1346 } 1347 1348 /******************************************************************************* 1349 * Restore EL2 sysreg context 1350 ******************************************************************************/ 1351 void cm_el2_sysregs_context_restore(uint32_t security_state) 1352 { 1353 cpu_context_t *ctx; 1354 el2_sysregs_t *el2_sysregs_ctx; 1355 1356 ctx = cm_get_context(security_state); 1357 assert(ctx != NULL); 1358 1359 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1360 1361 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1362 el2_sysregs_context_restore_gic(el2_sysregs_ctx); 1363 1364 if (is_feat_mte_supported()) { 1365 write_tfsr_el2(read_el2_ctx_mte(el2_sysregs_ctx, tfsr_el2)); 1366 } 1367 1368 #if CTX_INCLUDE_MPAM_REGS 1369 if (is_feat_mpam_supported()) { 1370 mpam_t *mpam_ctx = get_mpam_ctx(ctx); 1371 el2_sysregs_context_restore_mpam(mpam_ctx); 1372 } 1373 #endif 1374 1375 if (is_feat_fgt_supported()) { 1376 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1377 } 1378 1379 if (is_feat_ecv_v2_supported()) { 1380 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1381 } 1382 1383 if (is_feat_vhe_supported()) { 1384 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1385 contextidr_el2)); 1386 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1387 } 1388 1389 if (is_feat_ras_supported()) { 1390 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1391 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1392 } 1393 1394 if (is_feat_nv2_supported()) { 1395 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1396 } 1397 1398 if (is_feat_trf_supported()) { 1399 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1400 } 1401 1402 if (is_feat_csv2_2_supported()) { 1403 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1404 scxtnum_el2)); 1405 } 1406 1407 if (is_feat_hcx_supported()) { 1408 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1409 } 1410 1411 if (is_feat_tcr2_supported()) { 1412 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1413 } 1414 1415 if (is_feat_sxpie_supported()) { 1416 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1417 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1418 } 1419 1420 if (is_feat_sxpoe_supported()) { 1421 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1422 } 1423 1424 if (is_feat_s2pie_supported()) { 1425 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1426 } 1427 1428 if (is_feat_gcs_supported()) { 1429 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1430 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1431 } 1432 } 1433 #endif /* CTX_INCLUDE_EL2_REGS */ 1434 1435 /******************************************************************************* 1436 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1437 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1438 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1439 * cm_prepare_el3_exit function. 1440 ******************************************************************************/ 1441 void cm_prepare_el3_exit_ns(void) 1442 { 1443 #if CTX_INCLUDE_EL2_REGS 1444 #if ENABLE_ASSERTIONS 1445 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1446 assert(ctx != NULL); 1447 1448 /* Assert that EL2 is used. */ 1449 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1450 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1451 (el_implemented(2U) != EL_IMPL_NONE)); 1452 #endif /* ENABLE_ASSERTIONS */ 1453 1454 /* Restore EL2 and EL1 sysreg contexts */ 1455 cm_el2_sysregs_context_restore(NON_SECURE); 1456 cm_el1_sysregs_context_restore(NON_SECURE); 1457 cm_set_next_eret_context(NON_SECURE); 1458 #else 1459 cm_prepare_el3_exit(NON_SECURE); 1460 #endif /* CTX_INCLUDE_EL2_REGS */ 1461 } 1462 1463 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1464 { 1465 write_ctx_reg(ctx, CTX_SPSR_EL1, read_spsr_el1()); 1466 write_ctx_reg(ctx, CTX_ELR_EL1, read_elr_el1()); 1467 1468 #if !ERRATA_SPECULATIVE_AT 1469 write_ctx_reg(ctx, CTX_SCTLR_EL1, read_sctlr_el1()); 1470 write_ctx_reg(ctx, CTX_TCR_EL1, read_tcr_el1()); 1471 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1472 1473 write_ctx_reg(ctx, CTX_CPACR_EL1, read_cpacr_el1()); 1474 write_ctx_reg(ctx, CTX_CSSELR_EL1, read_csselr_el1()); 1475 write_ctx_reg(ctx, CTX_SP_EL1, read_sp_el1()); 1476 write_ctx_reg(ctx, CTX_ESR_EL1, read_esr_el1()); 1477 write_ctx_reg(ctx, CTX_TTBR0_EL1, read_ttbr0_el1()); 1478 write_ctx_reg(ctx, CTX_TTBR1_EL1, read_ttbr1_el1()); 1479 write_ctx_reg(ctx, CTX_MAIR_EL1, read_mair_el1()); 1480 write_ctx_reg(ctx, CTX_AMAIR_EL1, read_amair_el1()); 1481 write_ctx_reg(ctx, CTX_ACTLR_EL1, read_actlr_el1()); 1482 write_ctx_reg(ctx, CTX_TPIDR_EL1, read_tpidr_el1()); 1483 write_ctx_reg(ctx, CTX_TPIDR_EL0, read_tpidr_el0()); 1484 write_ctx_reg(ctx, CTX_TPIDRRO_EL0, read_tpidrro_el0()); 1485 write_ctx_reg(ctx, CTX_PAR_EL1, read_par_el1()); 1486 write_ctx_reg(ctx, CTX_FAR_EL1, read_far_el1()); 1487 write_ctx_reg(ctx, CTX_AFSR0_EL1, read_afsr0_el1()); 1488 write_ctx_reg(ctx, CTX_AFSR1_EL1, read_afsr1_el1()); 1489 write_ctx_reg(ctx, CTX_CONTEXTIDR_EL1, read_contextidr_el1()); 1490 write_ctx_reg(ctx, CTX_VBAR_EL1, read_vbar_el1()); 1491 1492 #if CTX_INCLUDE_AARCH32_REGS 1493 write_ctx_reg(ctx, CTX_SPSR_ABT, read_spsr_abt()); 1494 write_ctx_reg(ctx, CTX_SPSR_UND, read_spsr_und()); 1495 write_ctx_reg(ctx, CTX_SPSR_IRQ, read_spsr_irq()); 1496 write_ctx_reg(ctx, CTX_SPSR_FIQ, read_spsr_fiq()); 1497 write_ctx_reg(ctx, CTX_DACR32_EL2, read_dacr32_el2()); 1498 write_ctx_reg(ctx, CTX_IFSR32_EL2, read_ifsr32_el2()); 1499 #endif /* CTX_INCLUDE_AARCH32_REGS */ 1500 1501 #if NS_TIMER_SWITCH 1502 write_ctx_reg(ctx, CTX_CNTP_CTL_EL0, read_cntp_ctl_el0()); 1503 write_ctx_reg(ctx, CTX_CNTP_CVAL_EL0, read_cntp_cval_el0()); 1504 write_ctx_reg(ctx, CTX_CNTV_CTL_EL0, read_cntv_ctl_el0()); 1505 write_ctx_reg(ctx, CTX_CNTV_CVAL_EL0, read_cntv_cval_el0()); 1506 write_ctx_reg(ctx, CTX_CNTKCTL_EL1, read_cntkctl_el1()); 1507 #endif /* NS_TIMER_SWITCH */ 1508 1509 #if ENABLE_FEAT_MTE 1510 write_ctx_reg(ctx, CTX_TFSRE0_EL1, read_tfsre0_el1()); 1511 write_ctx_reg(ctx, CTX_TFSR_EL1, read_tfsr_el1()); 1512 write_ctx_reg(ctx, CTX_RGSR_EL1, read_rgsr_el1()); 1513 write_ctx_reg(ctx, CTX_GCR_EL1, read_gcr_el1()); 1514 #endif /* ENABLE_FEAT_MTE */ 1515 1516 } 1517 1518 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1519 { 1520 write_spsr_el1(read_ctx_reg(ctx, CTX_SPSR_EL1)); 1521 write_elr_el1(read_ctx_reg(ctx, CTX_ELR_EL1)); 1522 1523 #if !ERRATA_SPECULATIVE_AT 1524 write_sctlr_el1(read_ctx_reg(ctx, CTX_SCTLR_EL1)); 1525 write_tcr_el1(read_ctx_reg(ctx, CTX_TCR_EL1)); 1526 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1527 1528 write_cpacr_el1(read_ctx_reg(ctx, CTX_CPACR_EL1)); 1529 write_csselr_el1(read_ctx_reg(ctx, CTX_CSSELR_EL1)); 1530 write_sp_el1(read_ctx_reg(ctx, CTX_SP_EL1)); 1531 write_esr_el1(read_ctx_reg(ctx, CTX_ESR_EL1)); 1532 write_ttbr0_el1(read_ctx_reg(ctx, CTX_TTBR0_EL1)); 1533 write_ttbr1_el1(read_ctx_reg(ctx, CTX_TTBR1_EL1)); 1534 write_mair_el1(read_ctx_reg(ctx, CTX_MAIR_EL1)); 1535 write_amair_el1(read_ctx_reg(ctx, CTX_AMAIR_EL1)); 1536 write_actlr_el1(read_ctx_reg(ctx, CTX_ACTLR_EL1)); 1537 write_tpidr_el1(read_ctx_reg(ctx, CTX_TPIDR_EL1)); 1538 write_tpidr_el0(read_ctx_reg(ctx, CTX_TPIDR_EL0)); 1539 write_tpidrro_el0(read_ctx_reg(ctx, CTX_TPIDRRO_EL0)); 1540 write_par_el1(read_ctx_reg(ctx, CTX_PAR_EL1)); 1541 write_far_el1(read_ctx_reg(ctx, CTX_FAR_EL1)); 1542 write_afsr0_el1(read_ctx_reg(ctx, CTX_AFSR0_EL1)); 1543 write_afsr1_el1(read_ctx_reg(ctx, CTX_AFSR1_EL1)); 1544 write_contextidr_el1(read_ctx_reg(ctx, CTX_CONTEXTIDR_EL1)); 1545 write_vbar_el1(read_ctx_reg(ctx, CTX_VBAR_EL1)); 1546 1547 #if CTX_INCLUDE_AARCH32_REGS 1548 write_spsr_abt(read_ctx_reg(ctx, CTX_SPSR_ABT)); 1549 write_spsr_und(read_ctx_reg(ctx, CTX_SPSR_UND)); 1550 write_spsr_irq(read_ctx_reg(ctx, CTX_SPSR_IRQ)); 1551 write_spsr_fiq(read_ctx_reg(ctx, CTX_SPSR_FIQ)); 1552 write_dacr32_el2(read_ctx_reg(ctx, CTX_DACR32_EL2)); 1553 write_ifsr32_el2(read_ctx_reg(ctx, CTX_IFSR32_EL2)); 1554 #endif /* CTX_INCLUDE_AARCH32_REGS */ 1555 1556 #if NS_TIMER_SWITCH 1557 write_cntp_ctl_el0(read_ctx_reg(ctx, CTX_CNTP_CTL_EL0)); 1558 write_cntp_cval_el0(read_ctx_reg(ctx, CTX_CNTP_CVAL_EL0)); 1559 write_cntv_ctl_el0(read_ctx_reg(ctx, CTX_CNTV_CTL_EL0)); 1560 write_cntv_cval_el0(read_ctx_reg(ctx, CTX_CNTV_CVAL_EL0)); 1561 write_cntkctl_el1(read_ctx_reg(ctx, CTX_CNTKCTL_EL1)); 1562 #endif /* NS_TIMER_SWITCH */ 1563 1564 #if ENABLE_FEAT_MTE 1565 write_tfsre0_el1(read_ctx_reg(ctx, CTX_TFSRE0_EL1)); 1566 write_tfsr_el1(read_ctx_reg(ctx, CTX_TFSR_EL1)); 1567 write_rgsr_el1(read_ctx_reg(ctx, CTX_RGSR_EL1)); 1568 write_gcr_el1(read_ctx_reg(ctx, CTX_GCR_EL1)); 1569 #endif /* ENABLE_FEAT_MTE */ 1570 1571 } 1572 1573 /******************************************************************************* 1574 * The next four functions are used by runtime services to save and restore 1575 * EL1 context on the 'cpu_context' structure for the specified security 1576 * state. 1577 ******************************************************************************/ 1578 void cm_el1_sysregs_context_save(uint32_t security_state) 1579 { 1580 cpu_context_t *ctx; 1581 1582 ctx = cm_get_context(security_state); 1583 assert(ctx != NULL); 1584 1585 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1586 1587 #if IMAGE_BL31 1588 if (security_state == SECURE) 1589 PUBLISH_EVENT(cm_exited_secure_world); 1590 else 1591 PUBLISH_EVENT(cm_exited_normal_world); 1592 #endif 1593 } 1594 1595 void cm_el1_sysregs_context_restore(uint32_t security_state) 1596 { 1597 cpu_context_t *ctx; 1598 1599 ctx = cm_get_context(security_state); 1600 assert(ctx != NULL); 1601 1602 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1603 1604 #if IMAGE_BL31 1605 if (security_state == SECURE) 1606 PUBLISH_EVENT(cm_entering_secure_world); 1607 else 1608 PUBLISH_EVENT(cm_entering_normal_world); 1609 #endif 1610 } 1611 1612 /******************************************************************************* 1613 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1614 * given security state with the given entrypoint 1615 ******************************************************************************/ 1616 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1617 { 1618 cpu_context_t *ctx; 1619 el3_state_t *state; 1620 1621 ctx = cm_get_context(security_state); 1622 assert(ctx != NULL); 1623 1624 /* Populate EL3 state so that ERET jumps to the correct entry */ 1625 state = get_el3state_ctx(ctx); 1626 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1627 } 1628 1629 /******************************************************************************* 1630 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1631 * pertaining to the given security state 1632 ******************************************************************************/ 1633 void cm_set_elr_spsr_el3(uint32_t security_state, 1634 uintptr_t entrypoint, uint32_t spsr) 1635 { 1636 cpu_context_t *ctx; 1637 el3_state_t *state; 1638 1639 ctx = cm_get_context(security_state); 1640 assert(ctx != NULL); 1641 1642 /* Populate EL3 state so that ERET jumps to the correct entry */ 1643 state = get_el3state_ctx(ctx); 1644 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1645 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1646 } 1647 1648 /******************************************************************************* 1649 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1650 * pertaining to the given security state using the value and bit position 1651 * specified in the parameters. It preserves all other bits. 1652 ******************************************************************************/ 1653 void cm_write_scr_el3_bit(uint32_t security_state, 1654 uint32_t bit_pos, 1655 uint32_t value) 1656 { 1657 cpu_context_t *ctx; 1658 el3_state_t *state; 1659 u_register_t scr_el3; 1660 1661 ctx = cm_get_context(security_state); 1662 assert(ctx != NULL); 1663 1664 /* Ensure that the bit position is a valid one */ 1665 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1666 1667 /* Ensure that the 'value' is only a bit wide */ 1668 assert(value <= 1U); 1669 1670 /* 1671 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1672 * and set it to its new value. 1673 */ 1674 state = get_el3state_ctx(ctx); 1675 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1676 scr_el3 &= ~(1UL << bit_pos); 1677 scr_el3 |= (u_register_t)value << bit_pos; 1678 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1679 } 1680 1681 /******************************************************************************* 1682 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1683 * given security state. 1684 ******************************************************************************/ 1685 u_register_t cm_get_scr_el3(uint32_t security_state) 1686 { 1687 cpu_context_t *ctx; 1688 el3_state_t *state; 1689 1690 ctx = cm_get_context(security_state); 1691 assert(ctx != NULL); 1692 1693 /* Populate EL3 state so that ERET jumps to the correct entry */ 1694 state = get_el3state_ctx(ctx); 1695 return read_ctx_reg(state, CTX_SCR_EL3); 1696 } 1697 1698 /******************************************************************************* 1699 * This function is used to program the context that's used for exception 1700 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1701 * the required security state 1702 ******************************************************************************/ 1703 void cm_set_next_eret_context(uint32_t security_state) 1704 { 1705 cpu_context_t *ctx; 1706 1707 ctx = cm_get_context(security_state); 1708 assert(ctx != NULL); 1709 1710 cm_set_next_context(ctx); 1711 } 1712