Merge changes from topic "gr/cpu_lib" into integration

* changes:
feat(cpus): add support for caddo cpu
feat(cpus): add support for veymont cpu

Merge changes Id711e387,I531a2ee1,Ic5b48514,I81f5f663,I6c529c13, ... into integration

* changes:
refactor(romlib): absorb WRAPPER_FLAGS into LDFLAGS
fix(build): simplify the -target options
fe

Merge changes Id711e387,I531a2ee1,Ic5b48514,I81f5f663,I6c529c13, ... into integration

* changes:
refactor(romlib): absorb WRAPPER_FLAGS into LDFLAGS
fix(build): simplify the -target options
feat(build): allow full LTO builds with clang
refactor(build): make sorting of sections generic
feat(build): use clang as a linker
fix(build): correctly detect that an option is missing with ld_option
feat(build): pass cflags to the linker when LTO is enabled

show more ...

Merge changes from topic "gr/spectre_bhb_updates" into integration

* changes:
fix(security): fix Neoverse V2 CVE-2022-23960
fix(security): fix Cortex-X3 CVE-2022-23960
fix(security): fix Corte

Merge changes from topic "gr/spectre_bhb_updates" into integration

* changes:
fix(security): fix Neoverse V2 CVE-2022-23960
fix(security): fix Cortex-X3 CVE-2022-23960
fix(security): fix Cortex-A715 CVE-2022-23960
fix(security): fix spectre bhb loop count for Cortex-A720

show more ...

feat(cpus): add support for caddo cpu

Add basic CPU library code to support Caddo CPU

Change-Id: I4b431771ebe6f23eb02f3301ff656cfcd4956f81
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

feat(cpus): add support for veymont cpu

Add basic CPU library code to support Veymont CPU

Change-Id: I44db5650e7c9cf8fcc368c935574f4702c373dae
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

feat(build): use clang as a linker

To support LTO, the gcc binary is used as a compiler, assembler, and
linker. Do the same for clang and enable LTO builds with it as a side
effect.

This simplifies

feat(build): use clang as a linker

To support LTO, the gcc binary is used as a compiler, assembler, and
linker. Do the same for clang and enable LTO builds with it as a side
effect.

This simplifies code quite a bit as the gcc/clang different is much
smaller. Support for ld/lld (if overriden with LD) is maintained.

This is a good time to convert tabs to spaces to conform to make's
expectations on syntax.

Change-Id: I6c529c1393f7e9e8046ed537f871fc3ad91d599a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

feat(build): pass cflags to the linker when LTO is enabled

Usually, both compiling and linking happen by calling the top level
gcc/clang binary. Also, both compilers quite specifically tell us to
pa

feat(build): pass cflags to the linker when LTO is enabled

Usually, both compiling and linking happen by calling the top level
gcc/clang binary. Also, both compilers quite specifically tell us to
pass the same flags to the compilation and linking stages when we enable
LTO. This is crucial for things like the undefined behaviour sanitiser.
Anecdotally, in working on this, there have been a fair few errors that
the compiler has only been able to catch due to warning flags being
passed to the linker and building with LTO.

This patch puts the contents of TF_CFLAGS into TF_LDFLAGS when LTO is
enabled. This is easier said than done, however, as we support building
with clang and linking with gcc (or vice versa), so CFLAGS that are
discovered for one will not work for the other. This patch works around
this by splitting all flags into a per-compiler variable. Then CFLAGS
and LDFLAGS get the contents of the correct one.

Some notable side effects: CPPFLAGS and TF_CFLAGS_$(ARCH) become empty
and are removed, although expanding them is kept as platforms set them.
Some flags become duplicate and are removed form TF_LDFLAGS (eg -O1).

The errata (--fix) flags are kept as-is but moved to cpu-ops.mk for
consistency. This is because they currently don't work with LTO and will
be addressed in a later patch.

Finally, ERROR_DEPRECATED's flags are also identical on all compilers so
don't maintain a difference.

Change-Id: I3630729ee5f474c09d4722cd0ede6845e1725d95
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

refactor: fix workaround order for Cortex-A720

One of the Cortex-A720 errata was below the CVE workaround, this
moves it up to the correct place.

Change-Id: I6770567a9580973ceedb5911f0a495391ef9e83

refactor: fix workaround order for Cortex-A720

One of the Cortex-A720 errata was below the CVE workaround, this
moves it up to the correct place.

Change-Id: I6770567a9580973ceedb5911f0a495391ef9e839
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(cpus): workaround for Cortex-A720 erratum 2729604

Cortex-A720 erratum 2729604 is a Cat B erratum that applies to
revisions r0p0 and r0p1, and is fixed in r0p2.

This workaround might impact perf

fix(cpus): workaround for Cortex-A720 erratum 2729604

Cortex-A720 erratum 2729604 is a Cat B erratum that applies to
revisions r0p0 and r0p1, and is fixed in r0p2.

This workaround might impact performance of workloads heavily
relying on floating point division or square root operations.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2439421

Change-Id: I4567d75ba9f17146d0d7bc5cdb622bb63efadc3c
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(cpus): workaround for Cortex-A720 erratum 3711910

Cortex-A720 erratum 3711910 is a Cat B erratum that applies to
revisions r0p0, r0p1 and r0p2, and is still open.

SDEN documentation:
https://de

fix(cpus): workaround for Cortex-A720 erratum 3711910

Cortex-A720 erratum 3711910 is a Cat B erratum that applies to
revisions r0p0, r0p1 and r0p2, and is still open.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2439421

Change-Id: Id65d5ba41b96648b07c09df77fb25cc4bdb50800
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(cpus): workaround for Neoverse-V2 erratum 3701771

Neoverse-V2 erratum 3701771 that applies to r0p0, r0p1, r0p2 is
still Open.

The workaround is for EL3 software that performs context save/resto

fix(cpus): workaround for Neoverse-V2 erratum 3701771

Neoverse-V2 erratum 3701771 that applies to r0p0, r0p1, r0p2 is
still Open.

The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.

The mitigation is implemented in commit 7455cd172 and this patch should be applied on top of it.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ic0ad68f7bd393bdc03343d5ba815adb23bf6a24d

show more ...

fix(security): fix Neoverse V2 CVE-2022-23960

Apply CVE-2022-23960 mitigation to Neoverse V2, revision r0p0 only.
Ref - https://developer.arm.com/documentation/110280/latest/

Change-Id: I859012281f

fix(security): fix Neoverse V2 CVE-2022-23960

Apply CVE-2022-23960 mitigation to Neoverse V2, revision r0p0 only.
Ref - https://developer.arm.com/documentation/110280/latest/

Change-Id: I859012281fc67243f050d27e364f27434389c0cf
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

fix(security): fix Cortex-X3 CVE-2022-23960

Apply CVE-2022-23960 mitigation to Cortex-X3, revision r1p0 and earlier only.
Ref - https://developer.arm.com/documentation/110280/latest/

Change-Id: I3d

fix(security): fix Cortex-X3 CVE-2022-23960

Apply CVE-2022-23960 mitigation to Cortex-X3, revision r1p0 and earlier only.
Ref - https://developer.arm.com/documentation/110280/latest/

Change-Id: I3d46fa70c80129ca0085d8245ee013f11a8842e3
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

fix(security): fix Cortex-A715 CVE-2022-23960

Apply CVE-2022-23960 mitigation to Cortex-A715, revision r1p0 and earlier only.
Ref - https://developer.arm.com/documentation/110280/latest/

Change-Id:

fix(security): fix Cortex-A715 CVE-2022-23960

Apply CVE-2022-23960 mitigation to Cortex-A715, revision r1p0 and earlier only.
Ref - https://developer.arm.com/documentation/110280/latest/

Change-Id: Ib6b704733e474824772cb27bd048b1e179d90da9
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

fix(cpus): workaround for Neoverse-V2 erratum 3841324

Neoverse-V2 erratum 3841324 is a Cat B erratum that applies to
r0p0 and r0p1. It is fixed in r0p2.

This erratum can be avoided by setting CPUAC

fix(cpus): workaround for Neoverse-V2 erratum 3841324

Neoverse-V2 erratum 3841324 is a Cat B erratum that applies to
r0p0 and r0p1. It is fixed in r0p2.

This erratum can be avoided by setting CPUACTLR_EL1[1]
prior to enabling MMU. This bit will disable a branch predictor
power savings feature. Disabling this power feature
results in negligible power movement and no performance impact.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I9b3a5266103e5000d207c7a270c65455d0646102

show more ...

fix(cpus): workaround for Cortex-A510 erratum 3704847

Cortex-A510 erratum 3704847 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.

fix(cpus): workaround for Cortex-A510 erratum 3704847

Cortex-A510 erratum 3704847 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.

The workaround is to set bit 9 in CPUACTLR_EL1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/

Change-Id: I2c7c8da9c66471115b5bf8fb5c87d4de46ca265c
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(cpus): workaround for Cortex-A510 erratum 3672349

Cortex-A510 erratum 3672349 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.

fix(cpus): workaround for Cortex-A510 erratum 3672349

Cortex-A510 erratum 3672349 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.

The workaround is to clear the WFE_RET_CTRL and WFI_RET_CTRL fields
in CPUPWRCTLR_EL1 to disable full retention.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/

Change-Id: I9786ab8843a2eab45e650c6af50b6933481527ec
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(cpus): workaround for Cortex-A510 erratum 2420992

Cortex-A510 erratum 2420992 is a Cat B erratum that applies only to
revisions r1p0 and r1p1, and is fixed in r1p1.

The workaround is to set bit

fix(cpus): workaround for Cortex-A510 erratum 2420992

Cortex-A510 erratum 2420992 is a Cat B erratum that applies only to
revisions r1p0 and r1p1, and is fixed in r1p1.

The workaround is to set bit 3 in CPUACTLR3_EL1 which will have no
performance impact, but will increase power consumption by 0.3-0.5%.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/

Change-Id: Ia76ba2431d76f14c08b95a998806986190d682c3
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(cpus): workaround for Cortex-A510 erratum 2218134

Cortex-A510 erratum 2218134 is a Cat B erratum that applies only to
revision r1p0 and is fixed in r1p1.

The workaround is to set bit 43 in CPUA

fix(cpus): workaround for Cortex-A510 erratum 2218134

Cortex-A510 erratum 2218134 is a Cat B erratum that applies only to
revision r1p0 and is fixed in r1p1.

The workaround is to set bit 43 in CPUACTLR2_EL1 which will correct
the instruction fetch stream with no performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/

Change-Id: Ifec40dee2f7e42c56c9ed447b6b1997b170f9453
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(cpus): workaround for Cortex-A510 erratum 2169012

Cortex-A510 erratum 2169012 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.

This erratum ha

fix(cpus): workaround for Cortex-A510 erratum 2169012

Cortex-A510 erratum 2169012 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.

This erratum has an identical workaround to 1922240 and resolves
a similar issue, but that erratum only applies to r0p0 which is
not used in any production hardware, so it has been removed.

This workaround has a negligible performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/

Change-Id: Ifdd59c09e84252dc292600630d81d32986fd6c0c
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(cpus): workaround for Cortex-A510 erratum 2008766

Cortex-A510 erratum 2008766 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.

fix(cpus): workaround for Cortex-A510 erratum 2008766

Cortex-A510 erratum 2008766 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.

The workaround is to clear the ERXCTLR_EL1.ED bit before power
down, which will cause any detected errors during power down to
be ignored.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/

Change-Id: Id1aa0f2c518a055363c962f9abdb27e1ee8bff18
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(tc): fix c1_pro power down abandon

Following merge of [1] and [2] the fix to power down abandon for Arm
C1-Pro core got lost. Restore it.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-f

fix(tc): fix c1_pro power down abandon

Following merge of [1] and [2] the fix to power down abandon for Arm
C1-Pro core got lost. Restore it.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/43191
[2] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/42920

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I7da12e5ffc61248922adaf629eb52a5283993188

show more ...

chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/docu

chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/documentation/107771/0102/
C1-Ultra TRM: https://developer.arm.com/documentation/108014/0100/
C1-Premium TRM: https://developer.arm.com/documentation/109416/0100/
C1-Nano TRM: https://developer.arm.com/documentation/107753/0001/

[1]:
https://www.arm.com/product-filter?families=c1%20cpus
https://www.arm.com/products/mobile/compute-subsystems/lumex

Signed-off-by: Min Yao Ng <minyao.ng@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Id4b487ef6a6fd1b00b75b09c5d06d81bce50a15d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

Merge "feat(cpus): add pabandon support to Nevis" into integration

feat(cpus): add pabandon support to Nevis

Nevis' TRM says that a powerdown attempt may be abandoned for a handful
of reasons. Add support for handling this.

It also says that if the SME2 engine is

feat(cpus): add pabandon support to Nevis

Nevis' TRM says that a powerdown attempt may be abandoned for a handful
of reasons. Add support for handling this.

It also says that if the SME2 engine is not properly disconnected, then
a powerdown request will be rejected. Require ERRATA_SME_POWER_DOWN be
set to avoid this.

Just like Gelas/Travis, the 11.28 model doesn't reset the bit, so a
workaround is necessary.

Change-Id: I0d5de1b0e772f6b4d656e841fb4bcf8fd859f293
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...