fix(cpus): fix incorrect AMU trap settings for N2 CPU

The TAM bits of CPTR_EL2 and CPTR_EL3 are incorrectly set in the reset
handling sequence of the Neoverse N2 CPU. As these bits are set, any
acce

fix(cpus): fix incorrect AMU trap settings for N2 CPU

The TAM bits of CPTR_EL2 and CPTR_EL3 are incorrectly set in the reset
handling sequence of the Neoverse N2 CPU. As these bits are set, any
access of AMU registers from EL0/EL1 and EL2 respectively are
incorrectly trapped to a higher EL. Fix this by clearing the TAM bits in
both the CPTR_EL2 and CPTR_EL3 registers.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I357b16dfc7d7367b8a0c8086faac28f3e2866cd8

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Merge "fix(cpus): workaround for Neoverse V2 erratum 2618597" into integration

fix(cpus): workaround for Neoverse V2 erratum 2618597

Neoverse V2 erratum 2618597 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
disable the use

fix(cpus): workaround for Neoverse V2 erratum 2618597

Neoverse V2 erratum 2618597 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
disable the use of the Full Retention power mode in the core (setting
WFI_RET_CTRL and WFE_RET_CTRL in IMP_CPUPWRCTLR_EL1 to 0b000).

SDEN can be found here:
https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: I23a81275d1e40cae39e6897093d6cdd3e11c08ea
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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Merge "fix(cpus): workaround for Neoverse V2 erratum 2662553" into integration

Merge changes from topic "sm/errata" into integration

* changes:
fix(cpus): workaround for Cortex-A78C erratum 2743232
fix(cpus): workaround for Neoverse V1 erratum 2348377
fix(cpus): workarou

Merge changes from topic "sm/errata" into integration

* changes:
fix(cpus): workaround for Cortex-A78C erratum 2743232
fix(cpus): workaround for Neoverse V1 erratum 2348377
fix(cpus): workaround for Cortex-X3 erratum 2779509

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fix(errata): check for SCU before accessing DSU

The DSU contains system control registers in the SCU and L3 logic to
control the functionality of the cluster. If "DIRECT CONNECT" L3 memory
system va

fix(errata): check for SCU before accessing DSU

The DSU contains system control registers in the SCU and L3 logic to
control the functionality of the cluster. If "DIRECT CONNECT" L3 memory
system variant is used, there won't be any L3 cache, snoop filter, and
SCU logic present hence no system control register will be present.
Hence check SCU presence before accessing DSU register for DSU_2313941
errata.

(commit message taken from commit
942013e1dd57429432cd71cfe121d702e3c52465 by Pramod Kumar
<pramod.kumar@broadcom.com> just errata number changed)

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I38cee6085d6e49ba23de95b3de08bc98798ab2b3

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fix(cpus): workaround for Neoverse V2 erratum 2662553

Neoverse V2 erratum 2662553 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.
The workaround is to set L2 TQ size s

fix(cpus): workaround for Neoverse V2 erratum 2662553

Neoverse V2 erratum 2662553 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.
The workaround is to set L2 TQ size statically to it's full size.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: I3bc43e7299c17db8a6771a547515ffb2a172fa0f
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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fix(cpus): workaround for Cortex-A78C erratum 2743232

Cortex-A78C erratum 2743232 is a Cat B erratum that applies
to revisions r0p1 and r0p2 and is still open.
The workaround is to set CPUACTLR5_EL1

fix(cpus): workaround for Cortex-A78C erratum 2743232

Cortex-A78C erratum 2743232 is a Cat B erratum that applies
to revisions r0p1 and r0p2 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2004089/latest

Change-Id: Ic62579c2dd69b7a8cbbeaa936f45b2cc9436439a
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for Neoverse V1 erratum 2348377

Neoverse V1 erratum 2348377 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL

fix(cpus): workaround for Neoverse V1 erratum 2348377

Neoverse V1 erratum 2348377 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL1[61] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401781/latest

Change-Id: Ica402494f78811c85e56a262e1f60b09915168fe
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for Cortex-X3 erratum 2779509

Cortex-X3 erratum 2779509 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is
to set chicken bit CPUA

fix(cpus): workaround for Cortex-X3 erratum 2779509

Cortex-X3 erratum 2779509 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is
to set chicken bit CPUACTLR3_EL1[47], this might have a small
impact on power and has negligible impact on performance.

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Change-Id: Id92dbae6f1f313b133ffaa018fbf9c078da55d75
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 2742423

Cortex-X2 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55

fix(cpus): workaround for Cortex-X2 erratum 2742423

Cortex-X2 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I03897dc2a7f908937612c2b66ce7a043c1b7575d
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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fix(cpus): workaround for Cortex-A710 erratum 2742423

Cortex-A710 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open. The workaround is to set
CPUACTLR5_EL1[5

fix(cpus): workaround for Cortex-A710 erratum 2742423

Cortex-A710 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open. The workaround is to set
CPUACTLR5_EL1[56:55] to 2'b01.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest

Change-Id: I4d9d3760491f1e6c59b2667c16d59b99cc7979f1
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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fix(cpus): workaround for Neoverse N2 erratum 2340933

Neoverse N2 erratum 2340933 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1. The workaround is to set
CPUACTLR5_EL1[61] to

fix(cpus): workaround for Neoverse N2 erratum 2340933

Neoverse N2 erratum 2340933 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1. The workaround is to set
CPUACTLR5_EL1[61] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest

Change-Id: I121add0dd35072c53392d33f049d893a5ff6354f
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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fix(cpus): workaround for Neoverse N2 erratum 2346952

Neoverse N2 erratum 2346952 is a Cat B erratum that applies to all
revisions <= r0p2 and is fixed in r0p3.
The workaround is to set L2 TQ size s

fix(cpus): workaround for Neoverse N2 erratum 2346952

Neoverse N2 erratum 2346952 is a Cat B erratum that applies to all
revisions <= r0p2 and is fixed in r0p3.
The workaround is to set L2 TQ size statically to it's full size.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest

Change-Id: I03c3cf1f951fbc906fdebcb99a523c5ac8ba055d
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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Merge "feat(cpus): add support for Travis CPU" into integration

Merge changes from topic "sm/err_errata" into integration

* changes:
fix(cpus): fix the rev-var of Neoverse-V1
fix(errata-abi): update the Neoverse-N2 errata ABI struct
fix(errata-abi): update

Merge changes from topic "sm/err_errata" into integration

* changes:
fix(cpus): fix the rev-var of Neoverse-V1
fix(errata-abi): update the Neoverse-N2 errata ABI struct
fix(errata-abi): update the neoverse-N1 errata ABI struct
fix(cpus): fix the rev-var of Cortex-X2
fix(errata-abi): update the Cortex-A78C errata ABI struct
fix(cpus): update the rev-var for Cortex-A78AE
fix(errata-abi): update the Cortex-A76 errata ABI struct
fix(cpus): fix the rev-var for Cortex-A710

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feat(cpus): add support for Travis CPU

Adding basic CPU library code to support Travis CPU

Change-Id: I3c85e9fab409325d213978888a8f6d6949291258
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.

feat(cpus): add support for Travis CPU

Adding basic CPU library code to support Travis CPU

Change-Id: I3c85e9fab409325d213978888a8f6d6949291258
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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fix(cpus): workaround for Cortex-A510 erratum 2080326

Cortex-A510 erratum 2080326 is a Cat B erratum that applies
to all revisions <= r0p2 and is fixed in r0p3.
The workaround sequence helps perform

fix(cpus): workaround for Cortex-A510 erratum 2080326

Cortex-A510 erratum 2080326 is a Cat B erratum that applies
to all revisions <= r0p2 and is fixed in r0p3.
The workaround sequence helps perform a DSB after each TLBI
instruction and can be applied only for version r0p2 and has
minimal performance impact.
The workaround is not applicable for versions < r0p2.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1873361/latest

Change-Id: Ib9bce8b711c25a79f7b2f891ae6f8b366fc80ddd
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): fix the rev-var of Neoverse-V1

Update the revision and variant information in the
errata ABI file, neoverse_v1.S file for erratum ID - 2294912
to match the revision and variant in the lat

fix(cpus): fix the rev-var of Neoverse-V1

Update the revision and variant information in the
errata ABI file, neoverse_v1.S file for erratum ID - 2294912
to match the revision and variant in the latest SDEN.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401781/latest

Change-Id: I38a0f53c3515860ba442b5c0872c8ab051fdda6f
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): fix the rev-var of Cortex-X2

Update the revision and variant information in the
errata ABI file, cortex_X2.S file for erratum ID - 2058056
to match the revision and variant in the latest

fix(cpus): fix the rev-var of Cortex-X2

Update the revision and variant information in the
errata ABI file, cortex_X2.S file for erratum ID - 2058056
to match the revision and variant in the latest SDEN.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I28ee39949d977c53d6f5243100f0c29bc3c0428c
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): update the rev-var for Cortex-A78AE

Update the revision and variant information in the
cortex_a78_ae.s and errata ABI file for erratum ID - 2376748
based on the latest SDEN.

SDEN documen

fix(cpus): update the rev-var for Cortex-A78AE

Update the revision and variant information in the
cortex_a78_ae.s and errata ABI file for erratum ID - 2376748
based on the latest SDEN.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707912/latest

Change-Id: I082aac41adf717b0d5d59046a8933a3f5a3de94f
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): fix the rev-var for Cortex-A710

Update the revision and variant information in the
errata ABI file, cortex_A710.S file for erratum ID - 2058056
and erratum ID - 2055002 to match the revis

fix(cpus): fix the rev-var for Cortex-A710

Update the revision and variant information in the
errata ABI file, cortex_A710.S file for erratum ID - 2058056
and erratum ID - 2055002 to match the revision and variant
in the latest SDEN.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest

Change-Id: Ie010dae90dabf8670f588a06f9a606cf41e22afa
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for Cortex-X3 erratum 2070301

Cortex-X3 erratum 2070301 is a Cat B erratum that applies to all
revisions <= r1p2 and is still open.
The workaround is to write the value 4'b1001

fix(cpus): workaround for Cortex-X3 erratum 2070301

Cortex-X3 erratum 2070301 is a Cat B erratum that applies to all
revisions <= r1p2 and is still open.
The workaround is to write the value 4'b1001 to the PF_MODE bits
in the IMP_CPUECTLR2_EL1 register. This places the data prefetcher
in the most conservative mode instead of disabling it.

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Change-Id: I337c4c7bb9221715aaf973a55d0154e1c7555768
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge changes from topic "errata" into integration

* changes:
fix(cpus): workaround for Neoverse V2 erratum 2743011
fix(cpus): workaround for Neoverse V2 erratum 2779510
fix(cpus): workaround

Merge changes from topic "errata" into integration

* changes:
fix(cpus): workaround for Neoverse V2 erratum 2743011
fix(cpus): workaround for Neoverse V2 erratum 2779510
fix(cpus): workaround for Neoverse V2 erratum 2719105
fix(cpus): workaround for Neoverse V2 erratum 2331132

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fix(cpus): update the fix for Cortex-A78AE erratum 1941500

This patch fixes the mitigation for erratum 1941500 for the
Cortex-A78AE CPUs. The right fix is to set the bit 8, whereas
the current code

fix(cpus): update the fix for Cortex-A78AE erratum 1941500

This patch fixes the mitigation for erratum 1941500 for the
Cortex-A78AE CPUs. The right fix is to set the bit 8, whereas
the current code clears it.

Reported-by: matthias.rosenfelder@nio.io
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ib7c3fddd567eeae6204756377e0f77a573c0a911

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