1 /* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef NEOVERSE_V2_H 8 #define NEOVERSE_V2_H 9 10 #define NEOVERSE_V2_MIDR U(0x410FD4F0) 11 12 /* Neoverse V2 loop count for CVE-2022-23960 mitigation */ 13 #define NEOVERSE_V2_BHB_LOOP_COUNT U(132) 14 15 /******************************************************************************* 16 * CPU Extended Control register specific definitions 17 ******************************************************************************/ 18 #define NEOVERSE_V2_CPUECTLR_EL1 S3_0_C15_C1_4 19 20 /******************************************************************************* 21 * CPU Power Control register specific definitions 22 ******************************************************************************/ 23 #define NEOVERSE_V2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 24 #define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 25 26 /******************************************************************************* 27 * CPU Extended Control register 2 specific definitions. 28 ******************************************************************************/ 29 #define NEOVERSE_V2_CPUECTLR2_EL1 S3_0_C15_C1_5 30 #define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) 31 #define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB U(11) 32 #define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) 33 #define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0) 34 #define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB U(0) 35 #define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH U(3) 36 37 /******************************************************************************* 38 * CPU Auxiliary Control register 2 specific definitions. 39 ******************************************************************************/ 40 #define NEOVERSE_V2_CPUACTLR2_EL1 S3_0_C15_C1_1 41 #define NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 42 43 /******************************************************************************* 44 * CPU Auxiliary Control register 3 specific definitions. 45 ******************************************************************************/ 46 #define NEOVERSE_V2_CPUACTLR3_EL1 S3_0_C15_C1_2 47 #define NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47) 48 49 /******************************************************************************* 50 * CPU Auxiliary Control register 5 specific definitions. 51 ******************************************************************************/ 52 #define NEOVERSE_V2_CPUACTLR5_EL1 S3_0_C15_C8_0 53 #define NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) 54 #define NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) 55 56 #endif /* NEOVERSE_V2_H */ 57