1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v2.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25workaround_reset_start neoverse_v2, ERRATUM(2331132), ERRATA_V2_2331132 26 sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 27 NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH 28workaround_reset_end neoverse_v2, ERRATUM(2331132) 29 30check_erratum_ls neoverse_v2, ERRATUM(2331132), CPU_REV(0, 2) 31 32workaround_reset_start neoverse_v2, ERRATUM(2662553), ERRATA_V2_2662553 33 sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL, \ 34 NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH 35workaround_reset_end neoverse_v2, ERRATUM(2662553) 36 37check_erratum_ls neoverse_v2, ERRATUM(2662553), CPU_REV(0, 1) 38 39workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105 40 sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 41workaround_reset_end neoverse_v2, ERRATUM(2719105) 42 43check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1) 44 45workaround_reset_start neoverse_v2, ERRATUM(2743011), ERRATA_V2_2743011 46 sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 47 sysreg_bit_clear NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 48workaround_reset_end neoverse_v2, ERRATUM(2743011) 49 50check_erratum_ls neoverse_v2, ERRATUM(2743011), CPU_REV(0, 1) 51 52workaround_reset_start neoverse_v2, ERRATUM(2779510), ERRATA_V2_2779510 53 sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 54workaround_reset_end neoverse_v2, ERRATUM(2779510) 55 56check_erratum_ls neoverse_v2, ERRATUM(2779510), CPU_REV(0, 1) 57 58workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 59 /* dsb before isb of power down sequence */ 60 dsb sy 61workaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 62 63check_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1) 64 65workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 66#if IMAGE_BL31 67 /* 68 * The Neoverse-V2 generic vectors are overridden to apply errata 69 * mitigation on exception entry from lower ELs. 70 */ 71 override_vector_table wa_cve_vbar_neoverse_v2 72#endif /* IMAGE_BL31 */ 73workaround_reset_end neoverse_v2, CVE(2022,23960) 74 75check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 76 77#if WORKAROUND_CVE_2022_23960 78 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2 79#endif /* WORKAROUND_CVE_2022_23960 */ 80 81 /* ---------------------------------------------------- 82 * HW will do the cache maintenance while powering down 83 * ---------------------------------------------------- 84 */ 85func neoverse_v2_core_pwr_dwn 86 /* --------------------------------------------------- 87 * Enable CPU power down bit in power control register 88 * --------------------------------------------------- 89 */ 90 sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 91 apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 92 93 isb 94 ret 95endfunc neoverse_v2_core_pwr_dwn 96 97cpu_reset_func_start neoverse_v2 98 /* Disable speculative loads */ 99 msr SSBS, xzr 100cpu_reset_func_end neoverse_v2 101 102errata_report_shim neoverse_v2 103 /* --------------------------------------------- 104 * This function provides Neoverse V2- 105 * specific register information for crash 106 * reporting. It needs to return with x6 107 * pointing to a list of register names in ascii 108 * and x8 - x15 having values of registers to be 109 * reported. 110 * --------------------------------------------- 111 */ 112.section .rodata.neoverse_v2_regs, "aS" 113neoverse_v2_regs: /* The ascii list of register names to be reported */ 114 .asciz "cpuectlr_el1", "" 115 116func neoverse_v2_cpu_reg_dump 117 adr x6, neoverse_v2_regs 118 mrs x8, NEOVERSE_V2_CPUECTLR_EL1 119 ret 120endfunc neoverse_v2_cpu_reg_dump 121 122declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \ 123 neoverse_v2_reset_func, \ 124 neoverse_v2_core_pwr_dwn 125