fix(cpus): workaround for Cortex-A710 erratum 1916945

Cortex-A710 erratum 1916945 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.

The workaround is to set CPUECTLR_

fix(cpus): workaround for Cortex-A710 erratum 1916945

Cortex-A710 erratum 1916945 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.

The workaround is to set CPUECTLR_EL1[8]. This has a slight
performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101

Change-Id: I54793492c527928d7f266165a31b8613de838e69
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-A710 erratum 1901946

Cortex-A710 erratum 1901946 is a Cat B erratum that applies
to revision r1p0 and is fixed in r2p0.

The workaround is to set CPUACTLR4_EL1[15].

fix(cpus): workaround for Cortex-A710 erratum 1901946

Cortex-A710 erratum 1901946 is a Cat B erratum that applies
to revision r1p0 and is fixed in r2p0.

The workaround is to set CPUACTLR4_EL1[15]. This has a slight
performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101

Change-Id: I703f0e6ee122e44a9bc284d90f1465039e3b40e4
Signed-off-by: John Powell <john.powell@arm.com>

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Merge "fix(errata): keep leading zeros in CVE ID prints" into integration

fix(cpus): drop esb from the Neoverse N1

An esb is only necessary when FEAT_IESB is not present in hardware but
FEAT_RAS is. When FEAT_RAS is present we rely on the fact that FEAT_IESB
will also be

fix(cpus): drop esb from the Neoverse N1

An esb is only necessary when FEAT_IESB is not present in hardware but
FEAT_RAS is. When FEAT_RAS is present we rely on the fact that FEAT_IESB
will also be present and an implicit esb will pre present on eret.

Well the N1 implements FEAT_RAS and FEAT_IESB and the platforms that use
it (n1sdp) enable the features in firmware. So the esb is redundant.
There are dynamic platforms where this may not necessarily be true,
however, the esb is in an erratum workaround which cannot be present in
these platforms.

Change-Id: I5775180ec61373cc5d1b9831e3fa0f2fbb19eab9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(errata): keep leading zeros in CVE ID prints

The errata printing function would drop leading zeros on CVE
numbers so this updates the format string to make sure they are
printed. This is to conf

fix(errata): keep leading zeros in CVE ID prints

The errata printing function would drop leading zeros on CVE
numbers so this updates the format string to make sure they are
printed. This is to conform to the CVE naming convention where
ID numbers of less than 4 digits are prepended with 0s up to 4
digits.

This also updates a confusing comment indicating that leading
zeros could be used to work around a potential issue if CVE and
erratum IDs clash. Values with leading zeros will be interpreted
as octal numbers which is not desirable behavior so this should
not be recommended. Realistically, a CVE ID and erratum ID being
the same is *extremely* unlikely since CVE ID start over each
year and are 4-5 digits for Arm, and Errata IDs are 6-7 digits.

Change-Id: Idf2be50cea6828a3d30c6e58fda477ec1398bc7c
Signed-off-by: John Powell <john.powell@arm.com>

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refactor(cpus): optimize CVE checking

This patch replaces the use of EXTRA functions
with using erratum entries check
to verify CVE mitigation application for some of
the SMCCC_ARCH_WORKAROUND_* cal

refactor(cpus): optimize CVE checking

This patch replaces the use of EXTRA functions
with using erratum entries check
to verify CVE mitigation application for some of
the SMCCC_ARCH_WORKAROUND_* calls.

Previously, EXTRA functions were individually implemented for
each SMCCC_ARCH_WORKAROUND_*, an approach that becomes unmanageable
with the increasing number of workarounds.
By looking up erratum entries for CVE check, the process is streamlined,
reducing overhead associated with creating and
maintaining EXTRA functions for each new workaround.

New Errata entries are created for SMC workarounds and
that is used to target cpus that are uniquely impacted
by SMC workarounds.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I873534e367a35c99461d0a616ff7bf856a0000af

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refactor(cpus): move errata check to common code

This patch centralizes some of the Errata ABI code
that could be used for checking if an Errata has been applied
to cpu library since the function is

refactor(cpus): move errata check to common code

This patch centralizes some of the Errata ABI code
that could be used for checking if an Errata has been applied
to cpu library since the function is mostly generic.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I2c6d4468f7125d4d99ccdebc5ea8f9e4390360cc

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fix(cpus): add missing add_erratum_entry

Errata 1286807 and 1165522 are missing an add_erratum_entry, which is required by the Errata ABI to report whether the errata are implemented or not.

Change

fix(cpus): add missing add_erratum_entry

Errata 1286807 and 1165522 are missing an add_erratum_entry, which is required by the Errata ABI to report whether the errata are implemented or not.

Change-Id: I19a484c73ac31a90b3ff1b219f647c88a1c81c6e
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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chore(cpus): remove in-order checks

Remove runtime in-order checks for Erratum and CVE's.
Fix out-of-order issues in CPU files found with CPU Erratum and CVE
static checker script run on entire fold

chore(cpus): remove in-order checks

Remove runtime in-order checks for Erratum and CVE's.
Fix out-of-order issues in CPU files found with CPU Erratum and CVE
static checker script run on entire folder `lib/cpus/aarch64/`.

Change-Id: Iee5a8cb49834e9f35c6c2f2a84065430ca1ec8a6
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A

fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A. The current workaround attempts to follow option 2 but
misapplies it. Specifically, it statically sets PF_MODE to
conservative, which is not the recommended approach. According to the
erratum documentation, PF_MODE should be configured in conservative
mode only when we disable data prefetcher however this is not done
in TF-A and thus the workaround is not needed in TF-A.

The static setting of PF_MODE in TF-A does not correctly address the
erratum and may introduce unnecessary performance degradation on
platforms that adopt it without fully understanding its implications.

To prevent incorrect or unintended use, the current implementation of
this erratum workaround should be removed from TF-A and not adopted by
platforms.

List of Impacted CPU's with Errata Numbers and reference to SDEN -

Cortex-A78 - 2132060 - https://developer.arm.com/documentation/SDEN1401784/latest
Cortex-A78C - 2132064 - https://developer.arm.com/documentation/SDEN-2004089/latest
Cortex-A710 - 2058056 - https://developer.arm.com/documentation/SDEN-1775101/latest
Cortex-X2 - 2058056 - https://developer.arm.com/documentation/SDEN-1775100/latest
Cortex-X3 - 2070301 - https://developer.arm.com/documentation/SDEN2055130/latest
Neoverse-N2 - 2138953 - https://developer.arm.com/documentation/SDEN-1982442/latest
Neoverse-V1 - 2108267 - https://developer.arm.com/documentation/SDEN-1401781/latest
Neoverse-V2 - 2331132 - https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: Icf4048508ae070b2df073cc46c63be058b2779df
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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chore(cpus): rearrange the errata and cve in order in Cortex-X4

Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Cortex-X4.

Change-

chore(cpus): rearrange the errata and cve in order in Cortex-X4

Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Cortex-X4.

Change-Id: Ic304c2f68e7d0b96bbb30760696b7bceabe1ae2d
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore(cpus): rearrange the errata and cve in order in Neoverse-V3

Patch sorts the errata IDs in ascending order and the CVE's
in ascending order based on the year and index for Neoverse-V3.

Change-

chore(cpus): rearrange the errata and cve in order in Neoverse-V3

Patch sorts the errata IDs in ascending order and the CVE's
in ascending order based on the year and index for Neoverse-V3.

Change-Id: I108eb2896e24c135d56e5096289766d777b48b48
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore(cpus): rearrange cve and errata order in Cortex-X3

Patch sorts the errata IDs in ascending order and the
CVE-2024-5660 in order based on the year and index
for Cortex-X3.

Change-Id: I2a4baebe

chore(cpus): rearrange cve and errata order in Cortex-X3

Patch sorts the errata IDs in ascending order and the
CVE-2024-5660 in order based on the year and index
for Cortex-X3.

Change-Id: I2a4baebe0c3133528c089d999bdffa8c992f4989
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore(cpus): fix cve order in Neoverse-V2

Patch rearranges CVE-2024-5660 in order based on
the year and index for Neoverse-V2.

Change-Id: I092a93ef3299fd733abae9c462c019f94d881413
Signed-off-by: So

chore(cpus): fix cve order in Neoverse-V2

Patch rearranges CVE-2024-5660 in order based on
the year and index for Neoverse-V2.

Change-Id: I092a93ef3299fd733abae9c462c019f94d881413
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore(cpus): rearrange the errata and cve in order in Cortex-A710

Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Cortex-A710.

Cha

chore(cpus): rearrange the errata and cve in order in Cortex-A710

Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Cortex-A710.

Change-Id: Ie7c2b77879f8fa5abb77204678e09cc759b10278
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore(cpus): rearrange the errata and cve order in Neoverse-N2

Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Neoverse N2.

Change

chore(cpus): rearrange the errata and cve order in Neoverse-N2

Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Neoverse N2.

Change-Id: Ieb4a8ab0030ea4e83efdef86a0ff1e2990b3e0dd
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore(cpus): rearrange cve in order in Cortex-X1

Patch rearranges CVE-2024-5660 in ascending order based on
the year and index for Cortex X1.

Change-Id: I0c4206e38f09b1f88ee95e8ce69d7e13b8a9bb2d
Si

chore(cpus): rearrange cve in order in Cortex-X1

Patch rearranges CVE-2024-5660 in ascending order based on
the year and index for Cortex X1.

Change-Id: I0c4206e38f09b1f88ee95e8ce69d7e13b8a9bb2d
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore(cpus): fix cve order in Neoverse-V1

This patch rearranges CVE-2024-5660 apply order in Neoverse-V1.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ice0b1c6efa913f885

chore(cpus): fix cve order in Neoverse-V1

This patch rearranges CVE-2024-5660 apply order in Neoverse-V1.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ice0b1c6efa913f88522fb33182b9cdc0e7723988

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chore(cpus): fix cve order in Cortex-X2

This patch rearranges CVE-2024-5660, erratum 2313941
and 3701772 apply order in Cortex-X2.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Chan

chore(cpus): fix cve order in Cortex-X2

This patch rearranges CVE-2024-5660, erratum 2313941
and 3701772 apply order in Cortex-X2.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ie74d7232a14f3cdd14c4d0ffb1ee91b537c491ea

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chore(cpus): fix cve order in Cortex-A78C

This patch rearranges CVE-2024-5660 apply order in Cortex-A78C.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I326be1da279bd34df

chore(cpus): fix cve order in Cortex-A78C

This patch rearranges CVE-2024-5660 apply order in Cortex-A78C.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I326be1da279bd34df8667f7e957fb4a2c6913ab9

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chore(cpus): fix cve order in Cortex-A78_AE

This patch rearranges CVE-2024-5660 apply order in Cortex-A78_AE.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Idfb076b798a84

chore(cpus): fix cve order in Cortex-A78_AE

This patch rearranges CVE-2024-5660 apply order in Cortex-A78_AE.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Idfb076b798a840847c00066bd062ee919369272f

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chore(cpus): fix cve order in Cortex-A78

This patch rearranges CVE-2024-5660 apply order in Cortex-A78.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: If80a0f95f82dbf69100

chore(cpus): fix cve order in Cortex-A78

This patch rearranges CVE-2024-5660 apply order in Cortex-A78.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: If80a0f95f82dbf69100a2687b06db2373a9e9832

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chore(cpus): fix cve order in Cortex-A77

This patch rearranges CVE-2024-5660 apply order in Cortex-A77.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I41d76268ce2248bfd36

chore(cpus): fix cve order in Cortex-A77

This patch rearranges CVE-2024-5660 apply order in Cortex-A77.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I41d76268ce2248bfd3600bbf6b89d16b6bdce8f0

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refactor(cpus): don't panic if errata out of order

Previously we have used enclosed the Errata ordering check
within the FEATURE_DETECTION flag as this flag is only
used for development purpose and

refactor(cpus): don't panic if errata out of order

Previously we have used enclosed the Errata ordering check
within the FEATURE_DETECTION flag as this flag is only
used for development purpose and it also enforces
ordering by causing a panic when the assert fails.
A simple warning message would suffice and hence this
patch removes the assert.

The erratum and cve ordering check is planned to be implemented
in static check at which point the warning will be taken out as well.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I0ffc40361985281163970ea5bc81ca0269b16442

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fix(errata): workaround for Cortex-A510 erratum 2971420

Cortex-A510 erratum 2971420 applies to revisions r0p1, r0p2, r0p3,
r1p0, r1p1, r1p2 and r1p3, and is still open.

Under some conditions, data

fix(errata): workaround for Cortex-A510 erratum 2971420

Cortex-A510 erratum 2971420 applies to revisions r0p1, r0p2, r0p3,
r1p0, r1p1, r1p2 and r1p3, and is still open.

Under some conditions, data might be corrupted if Trace Buffer
Extension (TRBE) is enabled. The workaround is to disable trace
collection via TRBE by programming MDCR_EL3.NSTB[1] to the opposite
value of SCR_EL3.NS on a security state switch. Since we only enable
TRBE for non-secure world, the workaround is to disable TRBE by
setting the NSTB field to 00 so accesses are trapped to EL3 and
secure state owns the buffer.

SDEN: https://developer.arm.com/documentation/SDEN-1873361/latest/

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ia77051f6b64c726a8c50596c78f220d323ab7d97

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