Merge "Cortex-A55: workarounds for errata 1221012" into integration

Cortex-A55: workarounds for errata 1221012

The workaround is added to the Cortex-A55 cpu specific file. The
workaround is disabled by default and have to be explicitly enabled by
the platform integr

Cortex-A55: workarounds for errata 1221012

The workaround is added to the Cortex-A55 cpu specific file. The
workaround is disabled by default and have to be explicitly enabled by
the platform integrator.

Change-Id: I3e6fd10df6444122a8ee7d08058946ff1cc912f8
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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Add support for Branch Target Identification

This patch adds the functionality needed for platforms to provide
Branch Target Identification (BTI) extension, introduced to AArch64
in Armv8.5-A by add

Add support for Branch Target Identification

This patch adds the functionality needed for platforms to provide
Branch Target Identification (BTI) extension, introduced to AArch64
in Armv8.5-A by adding BTI instruction used to mark valid targets
for indirect branches. The patch sets new GP bit [50] to the stage 1
Translation Table Block and Page entries to denote guarded EL3 code
pages which will cause processor to trap instructions in protected
pages trying to perform an indirect branch to any instruction other
than BTI.
BTI feature is selected by BRANCH_PROTECTION option which supersedes
the previous ENABLE_PAUTH used for Armv8.3-A Pointer Authentication
and is disabled by default. Enabling BTI requires compiler support
and was tested with GCC versions 9.0.0, 9.0.1 and 10.0.0.
The assembly macros and helpers are modified to accommodate the BTI
instruction.
This is an experimental feature.
Note. The previous ENABLE_PAUTH build option to enable PAuth in EL3
is now made as an internal flag and BRANCH_PROTECTION flag should be
used instead to enable Pointer Authentication.
Note. USE_LIBROM=1 option is currently not supported.

Change-Id: Ifaf4438609b16647dc79468b70cd1f47a623362e
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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Disable speculative loads only if SSBS is supported

Examine the ID_AA64PFR1_EL1 bits 7:4 to see if speculative
loads (SSBS) is implemented, before disabling speculative
loads.

Change-Id: I7607c45ed

Disable speculative loads only if SSBS is supported

Examine the ID_AA64PFR1_EL1 bits 7:4 to see if speculative
loads (SSBS) is implemented, before disabling speculative
loads.

Change-Id: I7607c45ed2889260d22a94f6fd9af804520acf67
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>

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Merge changes from topic "sm/fix_a76_errata" into integration

* changes:
Workaround for cortex-A76 errata 1286807
Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112

Workaround for cortex-A76 errata 1286807

The workaround for Cortex-A76 errata #1286807 is implemented
in this patch.

Change-Id: I6c15af962ac99ce223e009f6d299cefb41043bed
Signed-off-by: Soby Mathew

Workaround for cortex-A76 errata 1286807

The workaround for Cortex-A76 errata #1286807 is implemented
in this patch.

Change-Id: I6c15af962ac99ce223e009f6d299cefb41043bed
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112

The workarounds for errata 1257314, 1262606, 1262888 and 1275112 are
added to the Cortex-A76 cpu specific file. The workarounds

Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112

The workarounds for errata 1257314, 1262606, 1262888 and 1275112 are
added to the Cortex-A76 cpu specific file. The workarounds are disabled
by default and have to be explicitly enabled by the platform integrator.

Change-Id: I70474927374cb67725f829d159ddde9ac4edc343
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Add compile-time errors for HW_ASSISTED_COHERENCY flag

This patch fixes this issue:
https://github.com/ARM-software/tf-issues/issues/660

The introduced changes are the following:

1) Some cores imp

Add compile-time errors for HW_ASSISTED_COHERENCY flag

This patch fixes this issue:
https://github.com/ARM-software/tf-issues/issues/660

The introduced changes are the following:

1) Some cores implement cache coherency maintenance operation on the
hardware level. For those cores, such as - but not only - the DynamIQ
cores, it is mandatory that TF-A is compiled with the
HW_ASSISTED_COHERENCY flag. If not, the core behaviour at runtime is
unpredictable. To prevent this, compile time checks have been added and
compilation errors are generated, if needed.

2) To enable this change for FVP, a logical separation has been done for
the core libraries. A system cannot contain cores of both groups, i.e.
cores that manage coherency on hardware and cores that don't do it. As
such, depending on the HW_ASSISTED_COHERENCY flag, FVP includes the
libraries only of the relevant cores.

3) The neoverse_e1.S file has been added to the FVP sources.

Change-Id: I787d15819b2add4ec0d238249e04bf0497dc12f3
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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Cortex-A53: Fix reporting of missing errata when not needed

Errata 819472, 824069, and 827319 are currently reported in a warning as
missing during boot for platforms that do not need them. Only war

Cortex-A53: Fix reporting of missing errata when not needed

Errata 819472, 824069, and 827319 are currently reported in a warning as
missing during boot for platforms that do not need them. Only warn when
the errata is needed for a given revision but not compiled in like other
errata workarounds.

Fixes: bd393704d2b1 ("Cortex-A53: Workarounds for 819472, 824069 and 827319")
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ifd757b3d0e73a9bd465b98dc20648b6c13397d8d

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Neoverse N1: Forces cacheable atomic to near

This patch forces all cacheable atomic instructions to be near, which
improves performance in highly contended parallelized use-cases.

Change-Id: I93fac

Neoverse N1: Forces cacheable atomic to near

This patch forces all cacheable atomic instructions to be near, which
improves performance in highly contended parallelized use-cases.

Change-Id: I93fac62847f4af8d5eaaf3b52318c30893e947d3
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

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DSU: Implement workaround for errata 798953

Under certain near idle conditions, DSU may miss response transfers on
the ACE master or Peripheral port, leading to deadlock. This workaround
disables hi

DSU: Implement workaround for errata 798953

Under certain near idle conditions, DSU may miss response transfers on
the ACE master or Peripheral port, leading to deadlock. This workaround
disables high-level clock gating of the DSU to prevent this.

Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

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DSU: Small fix and reformat on errata framework

Change-Id: I50708f6ccc33059fbfe6d36fd66351f0b894311f
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Cortex-A35: Implement workaround for errata 855472

Under specific conditions, the processor might issue an eviction and an
L2 cache clean operation to the interconnect in the wrong order. Set
the CP

Cortex-A35: Implement workaround for errata 855472

Under specific conditions, the processor might issue an eviction and an
L2 cache clean operation to the interconnect in the wrong order. Set
the CPUACTLR.ENDCCASCI bit to 1 to avoid this.

Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

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Add support for Cortex-A76AE CPU

Change-Id: I0a81f4ea94d41245cd5150de341b51fc70babffe
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Merge pull request #1887 from ambroise-arm/av/a76-cve

Cortex-A76: Optimize CVE_2018_3639 workaround

Merge pull request #1888 from jts-arm/zeus

Introduce preliminary support for Neoverse Zeus

Introduce preliminary support for Neoverse Zeus

Change-Id: If56d1e200a31bd716726d7fdc1cc0ae8a63ba3ee
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Apply variant 4 mitigation for Neoverse N1

This patch applies the new MSR instruction to directly set the
PSTATE.SSBS bit which controls speculative loads. This new instruction
is available at Neove

Apply variant 4 mitigation for Neoverse N1

This patch applies the new MSR instruction to directly set the
PSTATE.SSBS bit which controls speculative loads. This new instruction
is available at Neoverse N1 core so it's utilised.

Change-Id: Iee18a8b042c90fdb72d2b98f364dcfbb17510728
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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Cortex-A76: Optimize CVE_2018_3639 workaround

Switched from a static check to a runtime assert to make sure a
workaround is implemented for CVE_2018_3639.

This allows platforms that know they have

Cortex-A76: Optimize CVE_2018_3639 workaround

Switched from a static check to a runtime assert to make sure a
workaround is implemented for CVE_2018_3639.

This allows platforms that know they have the SSBS hardware workaround
in the CPU to compile out code under DYNAMIC_WORKAROUND_CVE_2018_3639.

The gain in memory size without the dynamic workaround is 4KB in bl31.

Change-Id: I61bb7d87c59964b0c7faac5d6bc7fc5c4651cbf3
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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Cortex-A76: fix spelling

Change-Id: I6adf7c14e8a974a7d40d51615b5e69eab1a7436f
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Merge pull request #1751 from vwadekar/tegra-scatter-file-support

Tegra scatter file support

Merge pull request #1849 from loumay-arm/lm/a73_errata

Cortex-A73: Implement workaround for errata 852427

Merge pull request #1845 from ambroise-arm/av/errata

Apply workarounds for errata of Cortex-A53, A55 and A57

Cortex-A73: Implement workaround for errata 852427

In AArch32, execution of 2 instructions with opposite condition code
might lead to either a data corruption or a CPU deadlock. Set the bit
12 of th

Cortex-A73: Implement workaround for errata 852427

In AArch32, execution of 2 instructions with opposite condition code
might lead to either a data corruption or a CPU deadlock. Set the bit
12 of the Diagnostic Register to prevent this.

Change-Id: I22b4f25fe933e2942fd785e411e7c0aa39d5c1f4
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

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Cortex-A53: Workarounds for 819472, 824069 and 827319

The workarounds for these errata are so closely related that it is
better to only have one patch to make it easier to understand.

Change-Id: I0

Cortex-A53: Workarounds for 819472, 824069 and 827319

The workarounds for these errata are so closely related that it is
better to only have one patch to make it easier to understand.

Change-Id: I0287fa69aefa8b72f884833f6ed0e7775ca834e9
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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