1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_H 8 #define ARCH_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * MIDR bit definitions 14 ******************************************************************************/ 15 #define MIDR_IMPL_MASK U(0xff) 16 #define MIDR_IMPL_SHIFT U(0x18) 17 #define MIDR_VAR_SHIFT U(20) 18 #define MIDR_VAR_BITS U(4) 19 #define MIDR_VAR_MASK U(0xf) 20 #define MIDR_REV_SHIFT U(0) 21 #define MIDR_REV_BITS U(4) 22 #define MIDR_REV_MASK U(0xf) 23 #define MIDR_PN_MASK U(0xfff) 24 #define MIDR_PN_SHIFT U(0x4) 25 26 /******************************************************************************* 27 * MPIDR macros 28 ******************************************************************************/ 29 #define MPIDR_MT_MASK (ULL(1) << 24) 30 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 31 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 32 #define MPIDR_AFFINITY_BITS U(8) 33 #define MPIDR_AFFLVL_MASK ULL(0xff) 34 #define MPIDR_AFF0_SHIFT U(0) 35 #define MPIDR_AFF1_SHIFT U(8) 36 #define MPIDR_AFF2_SHIFT U(16) 37 #define MPIDR_AFF3_SHIFT U(32) 38 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 39 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 40 #define MPIDR_AFFLVL_SHIFT U(3) 41 #define MPIDR_AFFLVL0 ULL(0x0) 42 #define MPIDR_AFFLVL1 ULL(0x1) 43 #define MPIDR_AFFLVL2 ULL(0x2) 44 #define MPIDR_AFFLVL3 ULL(0x3) 45 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 46 #define MPIDR_AFFLVL0_VAL(mpidr) \ 47 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 48 #define MPIDR_AFFLVL1_VAL(mpidr) \ 49 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 50 #define MPIDR_AFFLVL2_VAL(mpidr) \ 51 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 52 #define MPIDR_AFFLVL3_VAL(mpidr) \ 53 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 54 /* 55 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 56 * add one while using this macro to define array sizes. 57 * TODO: Support only the first 3 affinity levels for now. 58 */ 59 #define MPIDR_MAX_AFFLVL U(2) 60 61 #define MPID_MASK (MPIDR_MT_MASK | \ 62 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 66 67 #define MPIDR_AFF_ID(mpid, n) \ 68 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 69 70 /* 71 * An invalid MPID. This value can be used by functions that return an MPID to 72 * indicate an error. 73 */ 74 #define INVALID_MPID U(0xFFFFFFFF) 75 76 /******************************************************************************* 77 * Definitions for CPU system register interface to GICv3 78 ******************************************************************************/ 79 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 80 #define ICC_SGI1R S3_0_C12_C11_5 81 #define ICC_SRE_EL1 S3_0_C12_C12_5 82 #define ICC_SRE_EL2 S3_4_C12_C9_5 83 #define ICC_SRE_EL3 S3_6_C12_C12_5 84 #define ICC_CTLR_EL1 S3_0_C12_C12_4 85 #define ICC_CTLR_EL3 S3_6_C12_C12_4 86 #define ICC_PMR_EL1 S3_0_C4_C6_0 87 #define ICC_RPR_EL1 S3_0_C12_C11_3 88 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 89 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 90 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 91 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 92 #define ICC_IAR0_EL1 S3_0_c12_c8_0 93 #define ICC_IAR1_EL1 S3_0_c12_c12_0 94 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 95 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 96 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 97 98 /******************************************************************************* 99 * Generic timer memory mapped registers & offsets 100 ******************************************************************************/ 101 #define CNTCR_OFF U(0x000) 102 #define CNTFID_OFF U(0x020) 103 104 #define CNTCR_EN (U(1) << 0) 105 #define CNTCR_HDBG (U(1) << 1) 106 #define CNTCR_FCREQ(x) ((x) << 8) 107 108 /******************************************************************************* 109 * System register bit definitions 110 ******************************************************************************/ 111 /* CLIDR definitions */ 112 #define LOUIS_SHIFT U(21) 113 #define LOC_SHIFT U(24) 114 #define CLIDR_FIELD_WIDTH U(3) 115 116 /* CSSELR definitions */ 117 #define LEVEL_SHIFT U(1) 118 119 /* Data cache set/way op type defines */ 120 #define DCISW U(0x0) 121 #define DCCISW U(0x1) 122 #define DCCSW U(0x2) 123 124 /* ID_AA64PFR0_EL1 definitions */ 125 #define ID_AA64PFR0_EL0_SHIFT U(0) 126 #define ID_AA64PFR0_EL1_SHIFT U(4) 127 #define ID_AA64PFR0_EL2_SHIFT U(8) 128 #define ID_AA64PFR0_EL3_SHIFT U(12) 129 #define ID_AA64PFR0_AMU_SHIFT U(44) 130 #define ID_AA64PFR0_AMU_LENGTH U(4) 131 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 132 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 133 #define ID_AA64PFR0_SVE_SHIFT U(32) 134 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 135 #define ID_AA64PFR0_SVE_LENGTH U(4) 136 #define ID_AA64PFR0_MPAM_SHIFT U(40) 137 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 138 #define ID_AA64PFR0_DIT_SHIFT U(48) 139 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 140 #define ID_AA64PFR0_DIT_LENGTH U(4) 141 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 142 #define ID_AA64PFR0_CSV2_SHIFT U(56) 143 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 144 #define ID_AA64PFR0_CSV2_LENGTH U(4) 145 146 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 147 #define ID_AA64DFR0_PMS_SHIFT U(32) 148 #define ID_AA64DFR0_PMS_LENGTH U(4) 149 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 150 151 #define EL_IMPL_NONE ULL(0) 152 #define EL_IMPL_A64ONLY ULL(1) 153 #define EL_IMPL_A64_A32 ULL(2) 154 155 #define ID_AA64PFR0_GIC_SHIFT U(24) 156 #define ID_AA64PFR0_GIC_WIDTH U(4) 157 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 158 159 /* ID_AA64ISAR1_EL1 definitions */ 160 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 161 #define ID_AA64ISAR1_GPI_SHIFT U(28) 162 #define ID_AA64ISAR1_GPI_WIDTH U(4) 163 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 164 #define ID_AA64ISAR1_GPA_SHIFT U(24) 165 #define ID_AA64ISAR1_GPA_WIDTH U(4) 166 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 167 #define ID_AA64ISAR1_API_SHIFT U(8) 168 #define ID_AA64ISAR1_API_WIDTH U(4) 169 #define ID_AA64ISAR1_API_MASK ULL(0xf) 170 #define ID_AA64ISAR1_APA_SHIFT U(4) 171 #define ID_AA64ISAR1_APA_WIDTH U(4) 172 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 173 174 /* ID_AA64MMFR0_EL1 definitions */ 175 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 176 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 177 178 #define PARANGE_0000 U(32) 179 #define PARANGE_0001 U(36) 180 #define PARANGE_0010 U(40) 181 #define PARANGE_0011 U(42) 182 #define PARANGE_0100 U(44) 183 #define PARANGE_0101 U(48) 184 #define PARANGE_0110 U(52) 185 186 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 187 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 188 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 189 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 190 191 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 192 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 193 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 194 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 195 196 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 197 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 198 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 199 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 200 201 /* ID_AA64MMFR2_EL1 definitions */ 202 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 203 204 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 205 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 206 207 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 208 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 209 210 /* ID_AA64PFR1_EL1 definitions */ 211 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 212 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 213 214 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 215 216 /* ID_PFR1_EL1 definitions */ 217 #define ID_PFR1_VIRTEXT_SHIFT U(12) 218 #define ID_PFR1_VIRTEXT_MASK U(0xf) 219 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 220 & ID_PFR1_VIRTEXT_MASK) 221 222 /* SCTLR definitions */ 223 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 224 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 225 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 226 227 #define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 228 (U(1) << 22) | (U(1) << 20) | (U(1) << 11)) 229 #define SCTLR_AARCH32_EL1_RES1 \ 230 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 231 (U(1) << 4) | (U(1) << 3)) 232 233 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 234 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 235 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 236 237 #define SCTLR_M_BIT (ULL(1) << 0) 238 #define SCTLR_A_BIT (ULL(1) << 1) 239 #define SCTLR_C_BIT (ULL(1) << 2) 240 #define SCTLR_SA_BIT (ULL(1) << 3) 241 #define SCTLR_SA0_BIT (ULL(1) << 4) 242 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 243 #define SCTLR_ITD_BIT (ULL(1) << 7) 244 #define SCTLR_SED_BIT (ULL(1) << 8) 245 #define SCTLR_UMA_BIT (ULL(1) << 9) 246 #define SCTLR_I_BIT (ULL(1) << 12) 247 #define SCTLR_V_BIT (ULL(1) << 13) 248 #define SCTLR_DZE_BIT (ULL(1) << 14) 249 #define SCTLR_UCT_BIT (ULL(1) << 15) 250 #define SCTLR_NTWI_BIT (ULL(1) << 16) 251 #define SCTLR_NTWE_BIT (ULL(1) << 18) 252 #define SCTLR_WXN_BIT (ULL(1) << 19) 253 #define SCTLR_UWXN_BIT (ULL(1) << 20) 254 #define SCTLR_IESB_BIT (ULL(1) << 21) 255 #define SCTLR_E0E_BIT (ULL(1) << 24) 256 #define SCTLR_EE_BIT (ULL(1) << 25) 257 #define SCTLR_UCI_BIT (ULL(1) << 26) 258 #define SCTLR_EnIA_BIT (ULL(1) << 31) 259 #define SCTLR_DSSBS_BIT (ULL(1) << 44) 260 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 261 262 /* CPACR_El1 definitions */ 263 #define CPACR_EL1_FPEN(x) ((x) << 20) 264 #define CPACR_EL1_FP_TRAP_EL0 U(0x1) 265 #define CPACR_EL1_FP_TRAP_ALL U(0x2) 266 #define CPACR_EL1_FP_TRAP_NONE U(0x3) 267 268 /* SCR definitions */ 269 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 270 #define SCR_FIEN_BIT (U(1) << 21) 271 #define SCR_API_BIT (U(1) << 17) 272 #define SCR_APK_BIT (U(1) << 16) 273 #define SCR_TWE_BIT (U(1) << 13) 274 #define SCR_TWI_BIT (U(1) << 12) 275 #define SCR_ST_BIT (U(1) << 11) 276 #define SCR_RW_BIT (U(1) << 10) 277 #define SCR_SIF_BIT (U(1) << 9) 278 #define SCR_HCE_BIT (U(1) << 8) 279 #define SCR_SMD_BIT (U(1) << 7) 280 #define SCR_EA_BIT (U(1) << 3) 281 #define SCR_FIQ_BIT (U(1) << 2) 282 #define SCR_IRQ_BIT (U(1) << 1) 283 #define SCR_NS_BIT (U(1) << 0) 284 #define SCR_VALID_BIT_MASK U(0x2f8f) 285 #define SCR_RESET_VAL SCR_RES1_BITS 286 287 /* MDCR_EL3 definitions */ 288 #define MDCR_SPD32(x) ((x) << 14) 289 #define MDCR_SPD32_LEGACY ULL(0x0) 290 #define MDCR_SPD32_DISABLE ULL(0x2) 291 #define MDCR_SPD32_ENABLE ULL(0x3) 292 #define MDCR_SDD_BIT (ULL(1) << 16) 293 #define MDCR_NSPB(x) ((x) << 12) 294 #define MDCR_NSPB_EL1 ULL(0x3) 295 #define MDCR_TDOSA_BIT (ULL(1) << 10) 296 #define MDCR_TDA_BIT (ULL(1) << 9) 297 #define MDCR_TPM_BIT (ULL(1) << 6) 298 #define MDCR_SCCD_BIT (ULL(1) << 23) 299 #define MDCR_EL3_RESET_VAL ULL(0x0) 300 301 /* MDCR_EL2 definitions */ 302 #define MDCR_EL2_TPMS (U(1) << 14) 303 #define MDCR_EL2_E2PB(x) ((x) << 12) 304 #define MDCR_EL2_E2PB_EL1 U(0x3) 305 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 306 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 307 #define MDCR_EL2_TDA_BIT (U(1) << 9) 308 #define MDCR_EL2_TDE_BIT (U(1) << 8) 309 #define MDCR_EL2_HPME_BIT (U(1) << 7) 310 #define MDCR_EL2_TPM_BIT (U(1) << 6) 311 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 312 #define MDCR_EL2_RESET_VAL U(0x0) 313 314 /* HSTR_EL2 definitions */ 315 #define HSTR_EL2_RESET_VAL U(0x0) 316 #define HSTR_EL2_T_MASK U(0xff) 317 318 /* CNTHP_CTL_EL2 definitions */ 319 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 320 #define CNTHP_CTL_RESET_VAL U(0x0) 321 322 /* VTTBR_EL2 definitions */ 323 #define VTTBR_RESET_VAL ULL(0x0) 324 #define VTTBR_VMID_MASK ULL(0xff) 325 #define VTTBR_VMID_SHIFT U(48) 326 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 327 #define VTTBR_BADDR_SHIFT U(0) 328 329 /* HCR definitions */ 330 #define HCR_API_BIT (ULL(1) << 41) 331 #define HCR_APK_BIT (ULL(1) << 40) 332 #define HCR_TGE_BIT (ULL(1) << 27) 333 #define HCR_RW_SHIFT U(31) 334 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 335 #define HCR_AMO_BIT (ULL(1) << 5) 336 #define HCR_IMO_BIT (ULL(1) << 4) 337 #define HCR_FMO_BIT (ULL(1) << 3) 338 339 /* ISR definitions */ 340 #define ISR_A_SHIFT U(8) 341 #define ISR_I_SHIFT U(7) 342 #define ISR_F_SHIFT U(6) 343 344 /* CNTHCTL_EL2 definitions */ 345 #define CNTHCTL_RESET_VAL U(0x0) 346 #define EVNTEN_BIT (U(1) << 2) 347 #define EL1PCEN_BIT (U(1) << 1) 348 #define EL1PCTEN_BIT (U(1) << 0) 349 350 /* CNTKCTL_EL1 definitions */ 351 #define EL0PTEN_BIT (U(1) << 9) 352 #define EL0VTEN_BIT (U(1) << 8) 353 #define EL0PCTEN_BIT (U(1) << 0) 354 #define EL0VCTEN_BIT (U(1) << 1) 355 #define EVNTEN_BIT (U(1) << 2) 356 #define EVNTDIR_BIT (U(1) << 3) 357 #define EVNTI_SHIFT U(4) 358 #define EVNTI_MASK U(0xf) 359 360 /* CPTR_EL3 definitions */ 361 #define TCPAC_BIT (U(1) << 31) 362 #define TAM_BIT (U(1) << 30) 363 #define TTA_BIT (U(1) << 20) 364 #define TFP_BIT (U(1) << 10) 365 #define CPTR_EZ_BIT (U(1) << 8) 366 #define CPTR_EL3_RESET_VAL U(0x0) 367 368 /* CPTR_EL2 definitions */ 369 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 370 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 371 #define CPTR_EL2_TAM_BIT (U(1) << 30) 372 #define CPTR_EL2_TTA_BIT (U(1) << 20) 373 #define CPTR_EL2_TFP_BIT (U(1) << 10) 374 #define CPTR_EL2_TZ_BIT (U(1) << 8) 375 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 376 377 /* CPSR/SPSR definitions */ 378 #define DAIF_FIQ_BIT (U(1) << 0) 379 #define DAIF_IRQ_BIT (U(1) << 1) 380 #define DAIF_ABT_BIT (U(1) << 2) 381 #define DAIF_DBG_BIT (U(1) << 3) 382 #define SPSR_DAIF_SHIFT U(6) 383 #define SPSR_DAIF_MASK U(0xf) 384 385 #define SPSR_AIF_SHIFT U(6) 386 #define SPSR_AIF_MASK U(0x7) 387 388 #define SPSR_E_SHIFT U(9) 389 #define SPSR_E_MASK U(0x1) 390 #define SPSR_E_LITTLE U(0x0) 391 #define SPSR_E_BIG U(0x1) 392 393 #define SPSR_T_SHIFT U(5) 394 #define SPSR_T_MASK U(0x1) 395 #define SPSR_T_ARM U(0x0) 396 #define SPSR_T_THUMB U(0x1) 397 398 #define SPSR_M_SHIFT U(4) 399 #define SPSR_M_MASK U(0x1) 400 #define SPSR_M_AARCH64 U(0x0) 401 #define SPSR_M_AARCH32 U(0x1) 402 403 #define DISABLE_ALL_EXCEPTIONS \ 404 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 405 406 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 407 408 /* 409 * RMR_EL3 definitions 410 */ 411 #define RMR_EL3_RR_BIT (U(1) << 1) 412 #define RMR_EL3_AA64_BIT (U(1) << 0) 413 414 /* 415 * HI-VECTOR address for AArch32 state 416 */ 417 #define HI_VECTOR_BASE U(0xFFFF0000) 418 419 /* 420 * TCR defintions 421 */ 422 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 423 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 424 #define TCR_EL1_IPS_SHIFT U(32) 425 #define TCR_EL2_PS_SHIFT U(16) 426 #define TCR_EL3_PS_SHIFT U(16) 427 428 #define TCR_TxSZ_MIN ULL(16) 429 #define TCR_TxSZ_MAX ULL(39) 430 #define TCR_TxSZ_MAX_TTST ULL(48) 431 432 /* (internal) physical address size bits in EL3/EL1 */ 433 #define TCR_PS_BITS_4GB ULL(0x0) 434 #define TCR_PS_BITS_64GB ULL(0x1) 435 #define TCR_PS_BITS_1TB ULL(0x2) 436 #define TCR_PS_BITS_4TB ULL(0x3) 437 #define TCR_PS_BITS_16TB ULL(0x4) 438 #define TCR_PS_BITS_256TB ULL(0x5) 439 440 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 441 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 442 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 443 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 444 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 445 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 446 447 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 448 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 449 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 450 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 451 452 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 453 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 454 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 455 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 456 457 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 458 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 459 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 460 461 #define TCR_TG0_SHIFT U(14) 462 #define TCR_TG0_MASK ULL(3) 463 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 464 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 465 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 466 467 #define TCR_EPD0_BIT (ULL(1) << 7) 468 #define TCR_EPD1_BIT (ULL(1) << 23) 469 470 #define MODE_SP_SHIFT U(0x0) 471 #define MODE_SP_MASK U(0x1) 472 #define MODE_SP_EL0 U(0x0) 473 #define MODE_SP_ELX U(0x1) 474 475 #define MODE_RW_SHIFT U(0x4) 476 #define MODE_RW_MASK U(0x1) 477 #define MODE_RW_64 U(0x0) 478 #define MODE_RW_32 U(0x1) 479 480 #define MODE_EL_SHIFT U(0x2) 481 #define MODE_EL_MASK U(0x3) 482 #define MODE_EL3 U(0x3) 483 #define MODE_EL2 U(0x2) 484 #define MODE_EL1 U(0x1) 485 #define MODE_EL0 U(0x0) 486 487 #define MODE32_SHIFT U(0) 488 #define MODE32_MASK U(0xf) 489 #define MODE32_usr U(0x0) 490 #define MODE32_fiq U(0x1) 491 #define MODE32_irq U(0x2) 492 #define MODE32_svc U(0x3) 493 #define MODE32_mon U(0x6) 494 #define MODE32_abt U(0x7) 495 #define MODE32_hyp U(0xa) 496 #define MODE32_und U(0xb) 497 #define MODE32_sys U(0xf) 498 499 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 500 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 501 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 502 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 503 504 #define SPSR_64(el, sp, daif) \ 505 ((MODE_RW_64 << MODE_RW_SHIFT) | \ 506 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 507 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 508 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) 509 510 #define SPSR_MODE32(mode, isa, endian, aif) \ 511 ((MODE_RW_32 << MODE_RW_SHIFT) | \ 512 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 513 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 514 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 515 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) 516 517 /* 518 * TTBR Definitions 519 */ 520 #define TTBR_CNP_BIT ULL(0x1) 521 522 /* 523 * CTR_EL0 definitions 524 */ 525 #define CTR_CWG_SHIFT U(24) 526 #define CTR_CWG_MASK U(0xf) 527 #define CTR_ERG_SHIFT U(20) 528 #define CTR_ERG_MASK U(0xf) 529 #define CTR_DMINLINE_SHIFT U(16) 530 #define CTR_DMINLINE_MASK U(0xf) 531 #define CTR_L1IP_SHIFT U(14) 532 #define CTR_L1IP_MASK U(0x3) 533 #define CTR_IMINLINE_SHIFT U(0) 534 #define CTR_IMINLINE_MASK U(0xf) 535 536 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 537 538 /* Physical timer control register bit fields shifts and masks */ 539 #define CNTP_CTL_ENABLE_SHIFT U(0) 540 #define CNTP_CTL_IMASK_SHIFT U(1) 541 #define CNTP_CTL_ISTATUS_SHIFT U(2) 542 543 #define CNTP_CTL_ENABLE_MASK U(1) 544 #define CNTP_CTL_IMASK_MASK U(1) 545 #define CNTP_CTL_ISTATUS_MASK U(1) 546 547 /* Exception Syndrome register bits and bobs */ 548 #define ESR_EC_SHIFT U(26) 549 #define ESR_EC_MASK U(0x3f) 550 #define ESR_EC_LENGTH U(6) 551 #define EC_UNKNOWN U(0x0) 552 #define EC_WFE_WFI U(0x1) 553 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 554 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 555 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 556 #define EC_AARCH32_CP14_LDC_STC U(0x6) 557 #define EC_FP_SIMD U(0x7) 558 #define EC_AARCH32_CP10_MRC U(0x8) 559 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 560 #define EC_ILLEGAL U(0xe) 561 #define EC_AARCH32_SVC U(0x11) 562 #define EC_AARCH32_HVC U(0x12) 563 #define EC_AARCH32_SMC U(0x13) 564 #define EC_AARCH64_SVC U(0x15) 565 #define EC_AARCH64_HVC U(0x16) 566 #define EC_AARCH64_SMC U(0x17) 567 #define EC_AARCH64_SYS U(0x18) 568 #define EC_IABORT_LOWER_EL U(0x20) 569 #define EC_IABORT_CUR_EL U(0x21) 570 #define EC_PC_ALIGN U(0x22) 571 #define EC_DABORT_LOWER_EL U(0x24) 572 #define EC_DABORT_CUR_EL U(0x25) 573 #define EC_SP_ALIGN U(0x26) 574 #define EC_AARCH32_FP U(0x28) 575 #define EC_AARCH64_FP U(0x2c) 576 #define EC_SERROR U(0x2f) 577 578 /* 579 * External Abort bit in Instruction and Data Aborts synchronous exception 580 * syndromes. 581 */ 582 #define ESR_ISS_EABORT_EA_BIT U(9) 583 584 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 585 586 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 587 #define RMR_RESET_REQUEST_SHIFT U(0x1) 588 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 589 590 /******************************************************************************* 591 * Definitions of register offsets, fields and macros for CPU system 592 * instructions. 593 ******************************************************************************/ 594 595 #define TLBI_ADDR_SHIFT U(12) 596 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 597 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 598 599 /******************************************************************************* 600 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 601 * system level implementation of the Generic Timer. 602 ******************************************************************************/ 603 #define CNTCTLBASE_CNTFRQ U(0x0) 604 #define CNTNSAR U(0x4) 605 #define CNTNSAR_NS_SHIFT(x) (x) 606 607 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 608 #define CNTACR_RPCT_SHIFT U(0x0) 609 #define CNTACR_RVCT_SHIFT U(0x1) 610 #define CNTACR_RFRQ_SHIFT U(0x2) 611 #define CNTACR_RVOFF_SHIFT U(0x3) 612 #define CNTACR_RWVT_SHIFT U(0x4) 613 #define CNTACR_RWPT_SHIFT U(0x5) 614 615 /******************************************************************************* 616 * Definitions of register offsets and fields in the CNTBaseN Frame of the 617 * system level implementation of the Generic Timer. 618 ******************************************************************************/ 619 /* Physical Count register. */ 620 #define CNTPCT_LO U(0x0) 621 /* Counter Frequency register. */ 622 #define CNTBASEN_CNTFRQ U(0x10) 623 /* Physical Timer CompareValue register. */ 624 #define CNTP_CVAL_LO U(0x20) 625 /* Physical Timer Control register. */ 626 #define CNTP_CTL U(0x2c) 627 628 /* PMCR_EL0 definitions */ 629 #define PMCR_EL0_RESET_VAL U(0x0) 630 #define PMCR_EL0_N_SHIFT U(11) 631 #define PMCR_EL0_N_MASK U(0x1f) 632 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 633 #define PMCR_EL0_LC_BIT (U(1) << 6) 634 #define PMCR_EL0_DP_BIT (U(1) << 5) 635 #define PMCR_EL0_X_BIT (U(1) << 4) 636 #define PMCR_EL0_D_BIT (U(1) << 3) 637 638 /******************************************************************************* 639 * Definitions for system register interface to SVE 640 ******************************************************************************/ 641 #define ZCR_EL3 S3_6_C1_C2_0 642 #define ZCR_EL2 S3_4_C1_C2_0 643 644 /* ZCR_EL3 definitions */ 645 #define ZCR_EL3_LEN_MASK U(0xf) 646 647 /* ZCR_EL2 definitions */ 648 #define ZCR_EL2_LEN_MASK U(0xf) 649 650 /******************************************************************************* 651 * Definitions of MAIR encodings for device and normal memory 652 ******************************************************************************/ 653 /* 654 * MAIR encodings for device memory attributes. 655 */ 656 #define MAIR_DEV_nGnRnE ULL(0x0) 657 #define MAIR_DEV_nGnRE ULL(0x4) 658 #define MAIR_DEV_nGRE ULL(0x8) 659 #define MAIR_DEV_GRE ULL(0xc) 660 661 /* 662 * MAIR encodings for normal memory attributes. 663 * 664 * Cache Policy 665 * WT: Write Through 666 * WB: Write Back 667 * NC: Non-Cacheable 668 * 669 * Transient Hint 670 * NTR: Non-Transient 671 * TR: Transient 672 * 673 * Allocation Policy 674 * RA: Read Allocate 675 * WA: Write Allocate 676 * RWA: Read and Write Allocate 677 * NA: No Allocation 678 */ 679 #define MAIR_NORM_WT_TR_WA ULL(0x1) 680 #define MAIR_NORM_WT_TR_RA ULL(0x2) 681 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 682 #define MAIR_NORM_NC ULL(0x4) 683 #define MAIR_NORM_WB_TR_WA ULL(0x5) 684 #define MAIR_NORM_WB_TR_RA ULL(0x6) 685 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 686 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 687 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 688 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 689 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 690 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 691 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 692 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 693 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 694 695 #define MAIR_NORM_OUTER_SHIFT U(4) 696 697 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 698 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 699 700 /* PAR_EL1 fields */ 701 #define PAR_F_SHIFT U(0) 702 #define PAR_F_MASK ULL(0x1) 703 #define PAR_ADDR_SHIFT U(12) 704 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 705 706 /******************************************************************************* 707 * Definitions for system register interface to SPE 708 ******************************************************************************/ 709 #define PMBLIMITR_EL1 S3_0_C9_C10_0 710 711 /******************************************************************************* 712 * Definitions for system register interface to MPAM 713 ******************************************************************************/ 714 #define MPAMIDR_EL1 S3_0_C10_C4_4 715 #define MPAM2_EL2 S3_4_C10_C5_0 716 #define MPAMHCR_EL2 S3_4_C10_C4_0 717 #define MPAM3_EL3 S3_6_C10_C5_0 718 719 /******************************************************************************* 720 * Definitions for system register interface to AMU for ARMv8.4 onwards 721 ******************************************************************************/ 722 #define AMCR_EL0 S3_3_C13_C2_0 723 #define AMCFGR_EL0 S3_3_C13_C2_1 724 #define AMCGCR_EL0 S3_3_C13_C2_2 725 #define AMUSERENR_EL0 S3_3_C13_C2_3 726 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 727 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 728 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 729 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 730 731 /* Activity Monitor Group 0 Event Counter Registers */ 732 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 733 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 734 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 735 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 736 737 /* Activity Monitor Group 0 Event Type Registers */ 738 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 739 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 740 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 741 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 742 743 /* Activity Monitor Group 1 Event Counter Registers */ 744 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 745 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 746 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 747 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 748 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 749 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 750 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 751 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 752 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 753 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 754 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 755 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 756 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 757 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 758 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 759 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 760 761 /* Activity Monitor Group 1 Event Type Registers */ 762 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 763 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 764 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 765 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 766 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 767 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 768 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 769 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 770 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 771 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 772 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 773 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 774 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 775 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 776 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 777 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 778 779 /* AMCGCR_EL0 definitions */ 780 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 781 #define AMCGCR_EL0_CG1NC_LENGTH U(8) 782 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 783 784 /* MPAM register definitions */ 785 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 786 787 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 788 789 /******************************************************************************* 790 * RAS system registers 791 ******************************************************************************/ 792 #define DISR_EL1 S3_0_C12_C1_1 793 #define DISR_A_BIT U(31) 794 795 #define ERRIDR_EL1 S3_0_C5_C3_0 796 #define ERRIDR_MASK U(0xffff) 797 798 #define ERRSELR_EL1 S3_0_C5_C3_1 799 800 /* System register access to Standard Error Record registers */ 801 #define ERXFR_EL1 S3_0_C5_C4_0 802 #define ERXCTLR_EL1 S3_0_C5_C4_1 803 #define ERXSTATUS_EL1 S3_0_C5_C4_2 804 #define ERXADDR_EL1 S3_0_C5_C4_3 805 #define ERXPFGF_EL1 S3_0_C5_C4_4 806 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 807 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 808 #define ERXMISC0_EL1 S3_0_C5_C5_0 809 #define ERXMISC1_EL1 S3_0_C5_C5_1 810 811 #define ERXCTLR_ED_BIT (U(1) << 0) 812 #define ERXCTLR_UE_BIT (U(1) << 4) 813 814 #define ERXPFGCTL_UC_BIT (U(1) << 1) 815 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 816 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 817 818 /******************************************************************************* 819 * Armv8.3 Pointer Authentication Registers 820 ******************************************************************************/ 821 #define APIAKeyLo_EL1 S3_0_C2_C1_0 822 #define APIAKeyHi_EL1 S3_0_C2_C1_1 823 #define APIBKeyLo_EL1 S3_0_C2_C1_2 824 #define APIBKeyHi_EL1 S3_0_C2_C1_3 825 #define APDAKeyLo_EL1 S3_0_C2_C2_0 826 #define APDAKeyHi_EL1 S3_0_C2_C2_1 827 #define APDBKeyLo_EL1 S3_0_C2_C2_2 828 #define APDBKeyHi_EL1 S3_0_C2_C2_3 829 #define APGAKeyLo_EL1 S3_0_C2_C3_0 830 #define APGAKeyHi_EL1 S3_0_C2_C3_1 831 832 /******************************************************************************* 833 * Armv8.4 Data Independent Timing Registers 834 ******************************************************************************/ 835 #define DIT S3_3_C4_C2_5 836 #define DIT_BIT BIT(24) 837 838 #endif /* ARCH_H */ 839