1/* 2 * Copyright (c) 2022-2023, Google LLC. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <asm_macros.S> 8#include <cortex_x1.h> 9#include <cpu_macros.S> 10#include "wa_cve_2022_23960_bhb_vector.S" 11 12/* Hardware handled coherency */ 13#if HW_ASSISTED_COHERENCY == 0 14#error "Cortex-X1 must be compiled with HW_ASSISTED_COHERENCY enabled" 15#endif 16 17/* 64-bit only core */ 18#if CTX_INCLUDE_AARCH32_REGS == 1 19#error "Cortex-X1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 20#endif 21 22#if WORKAROUND_CVE_2022_23960 23 wa_cve_2022_23960_bhb_vector_table CORTEX_X1_BHB_LOOP_COUNT, cortex_x1 24#endif /* WORKAROUND_CVE_2022_23960 */ 25 26workaround_reset_start cortex_x1, ERRATUM(1688305), ERRATA_X1_1688305 27 mrs x0, CORTEX_X1_ACTLR2_EL1 28 orr x0, x0, #BIT(1) 29 msr CORTEX_X1_ACTLR2_EL1, x0 30workaround_reset_end cortex_x1, ERRATUM(1688305) 31 32check_erratum_ls cortex_x1, ERRATUM(1688305), CPU_REV(1, 0) 33 34workaround_reset_start cortex_x1, ERRATUM(1821534), ERRATA_X1_1821534 35 mrs x1, CORTEX_X1_ACTLR2_EL1 36 orr x1, x1, #BIT(2) 37 msr CORTEX_X1_ACTLR2_EL1, x1 38workaround_reset_end cortex_x1, ERRATUM(1821534) 39 40check_erratum_ls cortex_x1, ERRATUM(1821534), CPU_REV(1, 0) 41 42workaround_reset_start cortex_x1, ERRATUM(1827429), ERRATA_X1_1827429 43 mrs x0, CORTEX_X1_CPUECTLR_EL1 44 orr x0, x0, #BIT(53) 45 msr CORTEX_X1_CPUECTLR_EL1, x0 46workaround_reset_end cortex_x1, ERRATUM(1827429) 47 48check_erratum_ls cortex_x1, ERRATUM(1827429), CPU_REV(1, 0) 49 50check_erratum_chosen cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 51 52workaround_reset_start cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 53#if IMAGE_BL31 54 /* 55 * The Cortex-X1 generic vectors are overridden to apply errata 56 * mitigation on exception entry from lower ELs. 57 */ 58 adr x0, wa_cve_vbar_cortex_x1 59 msr vbar_el3, x0 60#endif /* IMAGE_BL31 */ 61workaround_reset_end cortex_x1, CVE(2022, 23960) 62 63cpu_reset_func_start cortex_x1 64cpu_reset_func_end cortex_x1 65 66 /* --------------------------------------------- 67 * HW will do the cache maintenance while powering down 68 * --------------------------------------------- 69 */ 70func cortex_x1_core_pwr_dwn 71 /* --------------------------------------------- 72 * Enable CPU power down bit in power control register 73 * --------------------------------------------- 74 */ 75 mrs x0, CORTEX_X1_CPUPWRCTLR_EL1 76 orr x0, x0, #CORTEX_X1_CORE_PWRDN_EN_MASK 77 msr CORTEX_X1_CPUPWRCTLR_EL1, x0 78 isb 79 ret 80endfunc cortex_x1_core_pwr_dwn 81 82errata_report_shim cortex_x1 83 84 /* --------------------------------------------- 85 * This function provides Cortex X1 specific 86 * register information for crash reporting. 87 * It needs to return with x6 pointing to 88 * a list of register names in ascii and 89 * x8 - x15 having values of registers to be 90 * reported. 91 * --------------------------------------------- 92 */ 93.section .rodata.cortex_x1_regs, "aS" 94cortex_x1_regs: /* The ascii list of register names to be reported */ 95 .asciz "cpuectlr_el1", "" 96 97func cortex_x1_cpu_reg_dump 98 adr x6, cortex_x1_regs 99 mrs x8, CORTEX_X1_CPUECTLR_EL1 100 ret 101endfunc cortex_x1_cpu_reg_dump 102 103declare_cpu_ops cortex_x1, CORTEX_X1_MIDR, \ 104 cortex_x1_reset_func, \ 105 cortex_x1_core_pwr_dwn 106