fix(nxp): driver crypto caam

Fix based on code review. Then, it was checked with NXP Flexbuild and
their fix has been imported.

Change-Id: Icae1fb08b07bca5d4f6771e92b48d9e2071da0ee
Signed-off-by: V

fix(nxp): driver crypto caam

Fix based on code review. Then, it was checked with NXP Flexbuild and
their fix has been imported.

Change-Id: Icae1fb08b07bca5d4f6771e92b48d9e2071da0ee
Signed-off-by: Vincent Jardin <vjardin@free.fr>

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feat(smcc): introduce a new vendor_el3 service for ACS SMC handler

In preparation to add support for the Architecture Compliance Suite
SMC services, reserve a SMC ID and introduce a handler function

feat(smcc): introduce a new vendor_el3 service for ACS SMC handler

In preparation to add support for the Architecture Compliance Suite
SMC services, reserve a SMC ID and introduce a handler function.
Currently, an empty placeholder function is added and future support
will be introduced for the handler support.

More info on System ACS, please refer below link,
https://developer.arm.com/Architectures/Architectural%20Compliance%20Suite

Signed-off-by: Nandan J <Nandan.J@arm.com>
Change-Id: Ib13ccae9d3829e3dcd1cd33c4a7f27efe1436d03

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fix(st-bsec): rename OTPSR field

Update the bit name in BSEC_OTPSR, align with the last ref manual.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I3b270406749f2f80d0d224

fix(st-bsec): rename OTPSR field

Update the bit name in BSEC_OTPSR, align with the last ref manual.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I3b270406749f2f80d0d2242bdf368d98d419d798

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fix(st-ddr): remove TODO in STM32MP2 driver

Remove useless ddr_get_io_calibration_val service.
Other items are deleted as they're useless on STM32MP2 series.

Signed-off-by: Nicolas Le Bayon <nicola

fix(st-ddr): remove TODO in STM32MP2 driver

Remove useless ddr_get_io_calibration_val service.
Other items are deleted as they're useless on STM32MP2 series.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I30bb18f156ff6dc06147987654363472a1e0182d

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fix(nxp): imx_trdc.h header guard

The header guard define is IMX_XRDC_H where everything
else is IMX_TRDC_H, gcc-15 complains about this so
update the define to what it should be.

Fixes: 293529100

fix(nxp): imx_trdc.h header guard

The header guard define is IMX_XRDC_H where everything
else is IMX_TRDC_H, gcc-15 complains about this so
update the define to what it should be.

Fixes: 293529100 ("feat(imx93): add the trdc driver")
Change-Id: I4767dc4d1c26ebe95d417be724f5cb848f54a524
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>

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Merge changes from topic "psa_key_id_mgmt" into integration

* changes:
feat(auth): extend REGISTER_CRYPTO_LIB calls
feat(bl): adding psa crypto - crypto_mod_finish()
feat(fvp): increase BL1 RW

Merge changes from topic "psa_key_id_mgmt" into integration

* changes:
feat(auth): extend REGISTER_CRYPTO_LIB calls
feat(bl): adding psa crypto - crypto_mod_finish()
feat(fvp): increase BL1 RW for PSA Crypto
feat(auth): mbedtls psa key id mgmt
feat(auth): add crypto_mod_finish() function
feat(auth): add update of current_pk_oid in auth
feat(auth): add util file for current pk_oid
feat(auth): increase mbedtls heap for PSA RSA
feat(auth): introducing auth.mk

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feat(auth): mbedtls psa key id mgmt

Currently the psa key is created and destroyed after each usage during
signature verification.

This redesign adds a key_cache to store the key ID, psa algorithm,

feat(auth): mbedtls psa key id mgmt

Currently the psa key is created and destroyed after each usage during
signature verification.

This redesign adds a key_cache to store the key ID, psa algorithm, and
key attributes associated with a particular pk_oid. This allows for the
psa key to be reused by each image that has the associated pk_oid.

The pk_oid of the image being authenticated is stored as the global
current_pk_oid variable, which is used during the psa crypto
verification stage to associate a key_cache entry with a particular
pk_oid.

Since the psa key is no longer destroyed after each usage, the psa keys
are therefore destroyed after all images have been loaded during each
boot phase in the new crypto_mod_finish() function that is registered
by the REGISTER_CRYPTO_LIB and enabled through the build option of
PSA_CRYTPO.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Iba330bc659a76493bd958673424efcc621bab1c4

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feat(auth): add crypto_mod_finish() function

Adding crypto_mod_finish() function to be run at the end of crypto usage
to cleanup.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Chan

feat(auth): add crypto_mod_finish() function

Adding crypto_mod_finish() function to be run at the end of crypto usage
to cleanup.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ib6d099ddaa278f293fe14b805070985522a85686

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feat(auth): add util file for current pk_oid

Adding new auth util file for the current_pk_oid and get and set
functions.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I9

feat(auth): add util file for current pk_oid

Adding new auth util file for the current_pk_oid and get and set
functions.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I91220f94d469c86f2e18570e13f1419125447288

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feat(auth): increase mbedtls heap for PSA RSA

Increase default mbedtls PSA crypto heap size for key id management
redesign where the key information is stored for reuse during
verification and needs

feat(auth): increase mbedtls heap for PSA RSA

Increase default mbedtls PSA crypto heap size for key id management
redesign where the key information is stored for reuse during
verification and needs more heap size for RSA keys.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I3afe0107a8e22ededd3eb4c0e1f635f18960d341

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Merge changes from topic "refactor_eip76_driver" into integration

* changes:
feat(marvell): add trng driver
revert(rambus-trng): remove ip-76 driver

feat(marvell): add trng driver

Armada-7K/8K and CN913x integrated the Rambus EIP-97 IP on CP11x die. It
supports to generate up to 4 32-bit random number in one shot.

This trivial driver provisions

feat(marvell): add trng driver

Armada-7K/8K and CN913x integrated the Rambus EIP-97 IP on CP11x die. It
supports to generate up to 4 32-bit random number in one shot.

This trivial driver provisions a simple API to read the random numbers
from hardware. It allows the bootloader to get one 32-bit or 64-bit
random number via SMC call to support KASLR.

Change-Id: I1707a85512ca163b8c7ab1644ff0f7e2fcf57344
Signed-off-by: Wilson Ding <dingwei@marvell.com>

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fix(errata): keep leading zeros in CVE ID prints

The errata printing function would drop leading zeros on CVE
numbers so this updates the format string to make sure they are
printed. This is to conf

fix(errata): keep leading zeros in CVE ID prints

The errata printing function would drop leading zeros on CVE
numbers so this updates the format string to make sure they are
printed. This is to conform to the CVE naming convention where
ID numbers of less than 4 digits are prepended with 0s up to 4
digits.

This also updates a confusing comment indicating that leading
zeros could be used to work around a potential issue if CVE and
erratum IDs clash. Values with leading zeros will be interpreted
as octal numbers which is not desirable behavior so this should
not be recommended. Realistically, a CVE ID and erratum ID being
the same is *extremely* unlikely since CVE ID start over each
year and are 4-5 digits for Arm, and Errata IDs are 6-7 digits.

Change-Id: Idf2be50cea6828a3d30c6e58fda477ec1398bc7c
Signed-off-by: John Powell <john.powell@arm.com>

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Merge "feat(spe): add support for FEAT_SPE_FDS" into integration

Merge changes I0b0443d5,Ic454a87a into integration

* changes:
fix(gic): quote the correct flag on error
feat(lib): add a generic EXTRACT macro

Merge changes from topic "fix_pmuv3p9_test" into integration

* changes:
fix(smccc): properly set RAS feature bit
fix(trng): allow FEAT_RNG_TRAP in dynamic fashion
feat(smccc): add FEAT_TWED to

Merge changes from topic "fix_pmuv3p9_test" into integration

* changes:
fix(smccc): properly set RAS feature bit
fix(trng): allow FEAT_RNG_TRAP in dynamic fashion
feat(smccc): add FEAT_TWED to ARCH_FEATURE_AVAILABILITY
feat(cpufeat): add support for PMUv3p9

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Merge changes from topic "hm/handoff-mb" into integration

* changes:
feat(arm): support boot info handoff and event log
fix(arm): update tsp_early_platform_setup prototype
fix(xilinx): update

Merge changes from topic "hm/handoff-mb" into integration

* changes:
feat(arm): support boot info handoff and event log
fix(arm): update tsp_early_platform_setup prototype
fix(xilinx): update tsp_early_platform_setup prototype
fix(socionext): update tsp_early_platform_setup prototype
fix(msm8916): update tsp_early_platform_setup prototype
feat(tsp): cascade boot arguments to platforms
feat(fvp): port event log to firmware handoff
feat(arm): port event log to firmware handoff
feat(fvp): increase bl2 mmap len for handoff
feat(measured-boot): add fw handoff event log utils

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Merge "feat(cpufeat): add support for FEAT_PAUTH_LR" into integration

feat(lib): add a generic EXTRACT macro

The EXTRACT macro is useful to extract a named field from a numeric
value, usually a register. It is functionally identical to the `ubfx`
instruction and uses

feat(lib): add a generic EXTRACT macro

The EXTRACT macro is useful to extract a named field from a numeric
value, usually a register. It is functionally identical to the `ubfx`
instruction and uses the same #defines (REG_FIELD_SHIFT and
REG_FIELD_WIDTH).

This is the same macro that we use in tftf. It works well there and is
quite useful for manipulating register fields concisely.

This macro replaces the EXTRACT_FIELD macro. Their function is
identical, however, EXTRACT allows for easier interoperation with the
`ubfx` instruction, makes code more similar to tftf, and is more
concise.

Change-Id: Ic454a87af5e5fac108c7b7cb6b6804ec65a8d0e8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "mmc_defines_fixes" into integration

* changes:
fix(mmc): fix the length of the response type
fix(mmc): fix the length of the ocr defines

Merge changes I005586ef,I0d4d74bc into integration

* changes:
fix(cpufeat): replace "bti" mnemonic with hint instructions
fix(cpufeat): improve xpaci wrapper

fix(cpufeat): replace "bti" mnemonic with hint instructions

Older GNU binutils version require to specify at least "armv8.5-a" for
the ARM architecture revision to accept "bti" instructions in the
a

fix(cpufeat): replace "bti" mnemonic with hint instructions

Older GNU binutils version require to specify at least "armv8.5-a" for
the ARM architecture revision to accept "bti" instructions in the
assembly code. Binutils v2.35 have relaxed this, since "bti" is in the
hint space, so is ignored on older cores and does NOT require a BTI
enabled core to execute.

To not exclude those older binutils versions (as shipped with Ubuntu
20.04), use the "hint" encoding for the "bti" instructions, which are
accepted regardless of the minimum architecture revision. Hide this
encoding in a macro, to make the "bti" usage more readable in the
source code.

Change-Id: I005586efd8974a3f2c7202896c881bb5fed07eea
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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fix(cpufeat): improve xpaci wrapper

Older toolchains seem to have trouble parsing a directive on the same
line as an instruction, so they choke on the separating semicolon:

/tmp/ccBwXW8I.s:93: Erro

fix(cpufeat): improve xpaci wrapper

Older toolchains seem to have trouble parsing a directive on the same
line as an instruction, so they choke on the separating semicolon:

/tmp/ccBwXW8I.s:93: Error: unknown architecture `armv8.3-a;'

Put the .arch directive on a line of its own, so that the assembler can
digest it.

Drop the comment on the way: xpaci is a FEAT_PAUTH instruction not
encoded in the hint space, so *every* toolchain needs to be allowed
ARMv8.3 level instructions, not just older ones.

Also we do not need to force x0 as the register, the compiler will pick
it automatically, so drop the register variable.

Change-Id: I0d4d74bcdac04aa86c565ad0455f62adf81febb5
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(spe): add support for FEAT_SPE_FDS

Allow access to PMSDSFR_EL1 register at NS-EL1 or NS-EL2 when
FEAT_SPE_FDS is implemented.

Change-Id: I538577cbfa5b5f242d5dbaeeace7b8e4ee6ffd03
Signed-off-by

feat(spe): add support for FEAT_SPE_FDS

Allow access to PMSDSFR_EL1 register at NS-EL1 or NS-EL2 when
FEAT_SPE_FDS is implemented.

Change-Id: I538577cbfa5b5f242d5dbaeeace7b8e4ee6ffd03
Signed-off-by: James Clark <james.clark2@arm.com>

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fix(arm): update tsp_early_platform_setup prototype

The prototype for tsp_early_platform_setup has been redefined. Update
the platform implementation to match the new function signature and
ensure c

fix(arm): update tsp_early_platform_setup prototype

The prototype for tsp_early_platform_setup has been redefined. Update
the platform implementation to match the new function signature and
ensure compatibility with the updated TSP interface. Also, update the
prototype for arm_tsp_early_platform_setup to make use of these
arguments in common code.

Change-Id: I3831776be58d6ebf672890d0f30bbbd1780976f7
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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