| e4f559ff | 16-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: Add PMIC support
If a PMIC companion chip is present on board, it has to be configured
for regulators supplies.
This check is done with board DT configuration.
Signed-off-by: Yann Gautier
stm32mp1: Add PMIC support
If a PMIC companion chip is present on board, it has to be configured
for regulators supplies.
This check is done with board DT configuration.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Pascal Paillet <p.paillet@st.com>
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|
| 6a339a49 | 13-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: Add GPIO support
The management of pinctrl nodes of device tree is also added.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed
stm32mp1: Add GPIO support
The management of pinctrl nodes of device tree is also added.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
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|
| 7839a050 | 24-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: Add clock and reset support
The clock driver is under dual license, BSD and GPLv2.
The clock driver uses device tree, so a minimal support for this is added.
The required files for driver
stm32mp1: Add clock and reset support
The clock driver is under dual license, BSD and GPLv2.
The clock driver uses device tree, so a minimal support for this is added.
The required files for driver and DTS files are in include/dt-bindings/.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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|
| 4353bb20 | 16-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
Introduce STMicroelectronics STM32MP1 platform
STM32MP1 is a microprocessor designed by STMicroelectronics,
based on a dual Arm Cortex-A7.
It is an Armv7-A platform, using dedicated code from TF-A.
Introduce STMicroelectronics STM32MP1 platform
STM32MP1 is a microprocessor designed by STMicroelectronics,
based on a dual Arm Cortex-A7.
It is an Armv7-A platform, using dedicated code from TF-A.
STM32MP1 uses BL2 compiled with BL2_AT_EL3.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Pascal Paillet <p.paillet@st.com>
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|
| d323af9e | 06-Jul-2018 |
Daniel Boulby <daniel.boulby@arm.com> |
Rework page table setup for varying number of mem regions
Change arm_setup_page_tables() to take a variable number of memory
regions. Remove coherent memory region from BL1, BL2 and BL2U as
their co
Rework page table setup for varying number of mem regions
Change arm_setup_page_tables() to take a variable number of memory
regions. Remove coherent memory region from BL1, BL2 and BL2U as
their coherent memory region doesn't contain anything and
therefore has a size of 0. Add check to ensure this
doesn't change without us knowing.
Change-Id: I790054e3b20b056dda1043a4a67bd7ac2d6a3bc0
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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|
| 790e6c5b | 24-Jul-2018 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1485 from jeenu-arm/ras
Double-fault and fatal error handling support |
| ecd62429 | 19-Jul-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
Arm platforms: Fix type mismatch for arm_pm_idle_states
This also gets rid of MISRA violations for Rule 8.3 and 8.4.
Change-Id: I45bba011b16f90953dd4b260fcd58381f978eedc
Signed-off-by: Jeenu Viswam
Arm platforms: Fix type mismatch for arm_pm_idle_states
This also gets rid of MISRA violations for Rule 8.3 and 8.4.
Change-Id: I45bba011b16f90953dd4b260fcd58381f978eedc
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
show more ...
|
| 6b7b0f36 | 17-Jul-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
PSCI: Fix MISRA defects in common and setup code
MISRA C-2012 Rules 10.1, 10.3, 17.8 and 20.7.
Change-Id: I3980bd2a1d845559af4bbe2887a0250d0506a064
Signed-off-by: Antonio Nino Diaz <antonio.ninodia
PSCI: Fix MISRA defects in common and setup code
MISRA C-2012 Rules 10.1, 10.3, 17.8 and 20.7.
Change-Id: I3980bd2a1d845559af4bbe2887a0250d0506a064
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
show more ...
|
| 2bc3dba9 | 18-Jul-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
PSCI: Fix MISRA defects in platform code
Fix violations of MISRA C-2012 Rules 10.1, 10.3, 13.3, 14.4, 17.7 and
17.8.
Change-Id: I6c9725e428b5752f1d80684ec29cb6c52a5c0c2d
Signed-off-by: Antonio Nino
PSCI: Fix MISRA defects in platform code
Fix violations of MISRA C-2012 Rules 10.1, 10.3, 13.3, 14.4, 17.7 and
17.8.
Change-Id: I6c9725e428b5752f1d80684ec29cb6c52a5c0c2d
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
show more ...
|
| 1083b2b3 | 20-Jul-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
PSCI: Fix types of definitions
Also change header guards to fix defects of MISRA C-2012 Rule 21.1.
Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57
Acked-by: Sumit Garg <sumit.garg@linaro.org>
PSCI: Fix types of definitions
Also change header guards to fix defects of MISRA C-2012 Rule 21.1.
Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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|
| bef9a10f | 18-Jul-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
PMF: Fix MISRA defects
Fix instances of MISRA C-2012 Rule 10.1 and 21.1.
Change-Id: I5676edede0703481e3635be0bc4a635df8e48f5e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
| 369742ec | 16-Jul-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
PSCI: Add missing function argument names
Fix MISRA C-2012 Rules 8.2 and 21.1.
Change-Id: I7f41fe76fe16399734d11847ab601ad8eb78df1a
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
| 97373c33 | 18-Jul-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
PSCI: Replace macros by static inline functions
Fix MISRA C-2012 Directive 4.9 and Rule 21.1 defects.
Change-Id: I96c216317d38741ee632d2640cd7b36e6723d5c2
Signed-off-by: Antonio Nino Diaz <antonio.
PSCI: Replace macros by static inline functions
Fix MISRA C-2012 Directive 4.9 and Rule 21.1 defects.
Change-Id: I96c216317d38741ee632d2640cd7b36e6723d5c2
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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|
| a0934217 | 20-Jul-2018 |
Daniel Boulby <daniel.boulby@arm.com> |
Increase BL2U stack size
BL2U is running out of stack during firmware update. Increase
stack size to prevent this
Change-Id: I9b1a4e237a00172c6738c84b455b3878ab184cb8
Signed-off-by: Daniel Boulby <
Increase BL2U stack size
BL2U is running out of stack during firmware update. Increase
stack size to prevent this
Change-Id: I9b1a4e237a00172c6738c84b455b3878ab184cb8
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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|
| f00119de | 18-Jul-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Fix check_[uptr/u32]_overflow() macros MISRA defects
Add missing parentheses to fix MISRA C-2012 Rule 12.1.
Also, the result of a comparison is an essentially boolean value, it
isn't needed to retu
Fix check_[uptr/u32]_overflow() macros MISRA defects
Add missing parentheses to fix MISRA C-2012 Rule 12.1.
Also, the result of a comparison is an essentially boolean value, it
isn't needed to return 1 or 0 depending on it.
Also, fix header guards (MISRA C-2012 Rule 21.1).
Change-Id: I90c0bcdeb2787c1ca659fc9a981808ece7958de3
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
show more ...
|
| 029f5a28 | 18-Jul-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Introduce UL(), L() and LL() macros
utils_def.h already has U() and ULL(), but not UL(), which is needed for
types like uinptr_t and u_register_t.
Also added L() and LL() for signed values.
Change
Introduce UL(), L() and LL() macros
utils_def.h already has U() and ULL(), but not UL(), which is needed for
types like uinptr_t and u_register_t.
Also added L() and LL() for signed values.
Change-Id: I0654df80d57149ff49507c52f1b27f3d500486a0
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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|
| ba0248b5 | 19-Jul-2018 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1450 from MISL-EBU-System-SW/marvell-support-v6
Marvell support for Armada 8K SoC family |
| 224e1aba | 19-Jul-2018 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1481 from antonio-nino-diaz-arm/an/xlat-refactor
xlat: More refactoring |
| 8ff0dfa7 | 19-Jul-2018 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1482 from sandrine-bailleux-arm/sb/fix-hcptr
Misc arch.h fixes and cleanup |
| b56dc2a9 | 17-May-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
RAS: Introduce handler for Uncontainable errors
Uncontainable errors are the most severe form of errors, which typically
mean that the system state can't be trusted any more. This further means
that
RAS: Introduce handler for Uncontainable errors
Uncontainable errors are the most severe form of errors, which typically
mean that the system state can't be trusted any more. This further means
that normal error recovery process can't be followed, and an orderly
shutdown of the system is often desirable.
This patch allows for the platform to define a handler for Uncontainable
errors received. Due to the nature of Uncontainable error, the handler
is expected to initiate an orderly shutdown of the system, and therefore
is not expected to return. A default implementation is added which falls
back to platform unhandled exception.
Also fix ras_arch.h header guards.
Change-Id: I072e336a391a0b382e77e627eb9e40729d488b55
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
show more ...
|
| 486f868b | 07-Jun-2018 |
Konstantin Porotchkin <kostap@marvell.com> |
plat: marvell: Add common ARMADA platform components
Add common Marvell ARMADA platform components.
This patch also includes common components for Marvell
ARMADA 8K platforms.
Change-Id: I42192fdc6
plat: marvell: Add common ARMADA platform components
Add common Marvell ARMADA platform components.
This patch also includes common components for Marvell
ARMADA 8K platforms.
Change-Id: I42192fdc6525a42e46b3ac2ad63c83db9bcbfeaf
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
show more ...
|
| f87e9449 | 26-Feb-2018 |
Konstantin Porotchkin <kostap@marvell.com> |
marvell: drivers: Add i2c driver
Add i2c driver for A8K SoC family.
Change-Id: I5932b2fce286d84fc3ad5a74c4c456001faa3196
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Por
marvell: drivers: Add i2c driver
Add i2c driver for A8K SoC family.
Change-Id: I5932b2fce286d84fc3ad5a74c4c456001faa3196
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
show more ...
|
| d5a6f86c | 26-Feb-2018 |
Konstantin Porotchkin <kostap@marvell.com> |
marvell: drivers: Add thermal driver
Add thermal driver for A8K SoC family.
The termal unit data is used by Marvell DRAM initialization
code for optimizing the memory controller configuration
Chang
marvell: drivers: Add thermal driver
Add thermal driver for A8K SoC family.
The termal unit data is used by Marvell DRAM initialization
code for optimizing the memory controller configuration
Change-Id: Iad92689fa6e4224a89d872e9aa015393abd9cf73
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
show more ...
|
| 152b0e47 | 26-Feb-2018 |
Konstantin Porotchkin <kostap@marvell.com> |
marvell: drivers: Add L3/system cache management drivers
Add LLC (L3) cache management drivers for Marvell SoCs
AP806, AP807 and AP810
Change-Id: Ic70710f9bc5b6b48395d62212df7011e2fbb5894
Signed-of
marvell: drivers: Add L3/system cache management drivers
Add LLC (L3) cache management drivers for Marvell SoCs
AP806, AP807 and AP810
Change-Id: Ic70710f9bc5b6b48395d62212df7011e2fbb5894
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
show more ...
|
| bc6206f7 | 05-Jul-2018 |
Konstantin Porotchkin <kostap@marvell.com> |
lib: cpu: Add L2 cache aux control register definition to CA72
Add definition of EL1 L2 Auxilary Control register to
Cortex A72 library headers.
Signed-off-by: Konstantin Porotchkin <kostap@marvell
lib: cpu: Add L2 cache aux control register definition to CA72
Add definition of EL1 L2 Auxilary Control register to
Cortex A72 library headers.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
show more ...
|