1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <mmio.h> 8 #include <utils_def.h> 9 #include <imx_aips.h> 10 #include <imx_regs.h> 11 12 static void imx_aips_set_default_access(struct aipstz_regs *aips_regs) 13 { 14 int i; 15 uintptr_t addr; 16 17 /* 18 * See section 4.7.7.1 AIPSTZ_MPR field descriptions 19 * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016 20 * 0111 -> 21 * 0: Write Access from master not buffered 22 * 1: Master is trusted for read access 23 * 1: Master is trsuted for write access 24 * 1: Access from master is not forced to user mode 25 */ 26 addr = (uintptr_t)&aips_regs->aipstz_mpr; 27 mmio_write_32(addr, 0x77777777); 28 29 /* 30 * Helpfully the OPACR registers have the logical inversion of the above 31 * See section 4.7.7.1 AIPSTZ_MPR field descriptions 32 * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016 33 * 0000 -> 34 * 0: Write Access to the peripheral is not buffered by AIPSTZ 35 * 0: The peripheral does not require supervisor priv to access 36 * 0: Master is trsuted for write access 37 * 0: Access from master is not forced to user mode 38 */ 39 for (i = 0; i < AIPSTZ_OAPCR_COUNT; i++) { 40 addr = (uintptr_t)&aips_regs->aipstz_opacr[i]; 41 mmio_write_32(addr, 0x00000000); 42 } 43 } 44 45 void imx_aips_init(void) 46 { 47 int i; 48 struct aipstz_regs *aips_regs[] = { 49 (struct aipstz_regs *)(AIPS1_BASE + AIPSTZ_CONFIG_OFFSET), 50 (struct aipstz_regs *)(AIPS2_BASE + AIPSTZ_CONFIG_OFFSET), 51 (struct aipstz_regs *)(AIPS3_BASE + AIPSTZ_CONFIG_OFFSET), 52 }; 53 54 for (i = 0; i < ARRAY_SIZE(aips_regs); i++) 55 imx_aips_set_default_access(aips_regs[i]); 56 } 57