| cc69cfd2 | 27-Mar-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
tzc: remove deprecated types
Types tzc_action_t and tzc_region_attributes_t are deprecated.
Change-Id: Ieefeb8521a0e1130f39d09b5c0d2728f05084773
Signed-off-by: Ambroise Vincent <ambroise.vincent@ar
tzc: remove deprecated types
Types tzc_action_t and tzc_region_attributes_t are deprecated.
Change-Id: Ieefeb8521a0e1130f39d09b5c0d2728f05084773
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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| be3991c0 | 27-Mar-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Console: remove deprecated finish_console_register
The old version of the macro is deprecated.
Commit cc5859ca19ff ("Multi-console: Deprecate the
`finish_console_register` macro") provides more det
Console: remove deprecated finish_console_register
The old version of the macro is deprecated.
Commit cc5859ca19ff ("Multi-console: Deprecate the
`finish_console_register` macro") provides more details.
Change-Id: I3d1cdf6496db7d8e6cfbb5804f508ff46ae7e67e
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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| fc3e1591 | 03-Apr-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1916 from antonio-nino-diaz-arm/an/spm-xlat
SPM: Some improvements to xlat handling code |
| 6de6965b | 27-Mar-2019 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
SPM: Move shim layer to TTBR1_EL1
This gives each Secure Partition complete freedom on its address space.
Previously, the memory used by the exception vectors was reserved and
couldn't be used. Also
SPM: Move shim layer to TTBR1_EL1
This gives each Secure Partition complete freedom on its address space.
Previously, the memory used by the exception vectors was reserved and
couldn't be used. Also, it always had to be mapped, forcing SPM to
generate translation tables that included the exception vectors as well
as the Partition memory regions. With this change, partitions can reduce
their address space size easily.
Change-Id: I67fb5e9bdf2870b73347f23bff702fab0a8f8711
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| b99f9224 | 28-Mar-2019 |
Remi Pommarel <repk@triplefau.lt> |
meson/gxl: Add support for SHA256 DMA engine
In order to configure and boot SCP, BL31 has to compute and send
the SHA-256 of the firmware data via scpi. Luckily Amlogic GXL SOC
has a DMA facility th
meson/gxl: Add support for SHA256 DMA engine
In order to configure and boot SCP, BL31 has to compute and send
the SHA-256 of the firmware data via scpi. Luckily Amlogic GXL SOC
has a DMA facility that could be used to offload SHA-256
computations. This adds basic support of this hardware SHA-256
engine.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
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| 609e053c | 13-Feb-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Remove several warnings reported with W=1
Improved support for W=1 compilation flag by solving missing-prototypes
and old-style-definition warnings.
The libraries are compiling with warnings (which
Remove several warnings reported with W=1
Improved support for W=1 compilation flag by solving missing-prototypes
and old-style-definition warnings.
The libraries are compiling with warnings (which turn into errors with
the Werror flag).
Outside of libraries, some warnings cannot be fixed without heavy
structural changes.
Change-Id: I1668cf99123ac4195c2a6a1d48945f7a64c67f16
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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| 75044d8b | 18-Mar-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge pull request #1894 from jts-arm/e1_midr
Fix MIDR_EL1 value for Neoverse E1 |
| c4187c9c | 15-Mar-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Fix wrong MIDR_EL1 value for Neoverse E1
Change-Id: I75ee39d78c81ecb528a671c0cfadfc2fe7b5d818
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> |
| 1fbb682a | 15-Mar-2019 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1888 from jts-arm/zeus
Introduce preliminary support for Neoverse Zeus |
| a4546e80 | 08-Oct-2018 |
John Tsichritzis <john.tsichritzis@arm.com> |
Introduce preliminary support for Neoverse Zeus
Change-Id: If56d1e200a31bd716726d7fdc1cc0ae8a63ba3ee
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> |
| 8074448f | 04-Mar-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Apply variant 4 mitigation for Neoverse N1
This patch applies the new MSR instruction to directly set the
PSTATE.SSBS bit which controls speculative loads. This new instruction
is available at Neove
Apply variant 4 mitigation for Neoverse N1
This patch applies the new MSR instruction to directly set the
PSTATE.SSBS bit which controls speculative loads. This new instruction
is available at Neoverse N1 core so it's utilised.
Change-Id: Iee18a8b042c90fdb72d2b98f364dcfbb17510728
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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| 0b64c194 | 28-Feb-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Cortex-A17: Implement workaround for errata 852421
Change-Id: Ic3004fc43229d63c5a59ca74c1837fb0604e1f33
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> |
| b9d20d0e | 13-Mar-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge pull request #1882 from ambroise-arm/av/a15-errata
Apply workarounds for errata of Cortex-A15 |
| b79239db | 13-Mar-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge pull request #1879 from pbeesley-arm/pb/todo-removal
Pb/todo removal |
| 77913d44 | 13-Mar-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge pull request #1858 from thloh85-intel/dwmmc_fixes
drivers: synopsys: Fix synopsys MMC driver |
| 5f2c690d | 05-Mar-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Cortex-A15: Implement workaround for errata 827671
This erratum can only be worked around on revisions >= r3p0 because the
register that needs to be accessed only exists in those revisions[1].
[1]
Cortex-A15: Implement workaround for errata 827671
This erratum can only be worked around on revisions >= r3p0 because the
register that needs to be accessed only exists in those revisions[1].
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html
Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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| cf6c30e0 | 07-Mar-2019 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
plat/arm: mhu: make mhu driver generic
MHU doorbell driver requires arm platform specific
macro "PLAT_CSS_MHU_BASE".
Rename it to "PLAT_MHUV2_BASE", so that platforms other than arm
can use generic
plat/arm: mhu: make mhu driver generic
MHU doorbell driver requires arm platform specific
macro "PLAT_CSS_MHU_BASE".
Rename it to "PLAT_MHUV2_BASE", so that platforms other than arm
can use generic MHU doorbell driver.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
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| 9a2fffb8 | 06-Mar-2019 |
Paul Beesley <paul.beesley@arm.com> |
drivers: Remove TODO from io_storage
This TODO was added five years ago so I assume that there is not
going to be a shutdown API added after all.
Change-Id: If0f4e2066454df773bd9bf41ed65d3a10248a2d
drivers: Remove TODO from io_storage
This TODO was added five years ago so I assume that there is not
going to be a shutdown API added after all.
Change-Id: If0f4e2066454df773bd9bf41ed65d3a10248a2d3
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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| 3d0f30bb | 12-Mar-2019 |
Tien Hock, Loh <tien.hock.loh@intel.com> |
drivers: synopsys: Fix synopsys MMC driver
There are some issues with synopsys MMC driver:
- CMD8 should not expect data (for SD)
- ACMD51 should expect data (Send SCR for SD)
- dw_prepare should no
drivers: synopsys: Fix synopsys MMC driver
There are some issues with synopsys MMC driver:
- CMD8 should not expect data (for SD)
- ACMD51 should expect data (Send SCR for SD)
- dw_prepare should not dictate size to be MMC_BLOCK_SIZE, block size is
now handled in the dw_prepare function
- after the CMD completes, when doing dw_read, we need to invalidate cache
and wait for the data transfer to complete
- Need to set FIFO threshold, otherwise DMA might never get the interrupt
to read or write
Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
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| 3c652a2d | 08-Mar-2019 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1863 from thloh85-intel/mmc_fixes
drivers: mmc: Fix some issues with MMC stack |
| a468e756 | 07-Mar-2019 |
Tien Hock, Loh <tien.hock.loh@intel.com> |
drivers: mmc: Fix some issues with MMC stack
Some bugs in MMC stack needs to be fixed:
- scr cannot be local as this will cause cache issue when invalidating
after the read DMA transfer is completed
drivers: mmc: Fix some issues with MMC stack
Some bugs in MMC stack needs to be fixed:
- scr cannot be local as this will cause cache issue when invalidating
after the read DMA transfer is completed
- ACMD41 needs to send voltage information in initialization, otherwise the
command is a query, thus will not initialize the controller
- when checking device state, retry until the retries counter goes to zero
before failing
Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
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| 6ecfda52 | 27-Feb-2019 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Ensure proper ID register is checked for feature detection
SSBS support is determined by checking ID_AA64PFR1_EL1 and not
ID_AA64PFR0_EL1.
Fixes ARM-Software/tf-issues#679
Change-Id: I8ecba13b8509
Ensure proper ID register is checked for feature detection
SSBS support is determined by checking ID_AA64PFR1_EL1 and not
ID_AA64PFR0_EL1.
Fixes ARM-Software/tf-issues#679
Change-Id: I8ecba13b850995ec6a6ede3c2a1e02e69a3a95db
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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| fb70e56d | 04-Mar-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1851 from antonio-nino-diaz-arm/an/pauth
Correctly check for support of Address Authentication |
| a4acc7f1 | 01-Mar-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1751 from vwadekar/tegra-scatter-file-support
Tegra scatter file support |
| 37118a1b | 01-Mar-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1849 from loumay-arm/lm/a73_errata
Cortex-A73: Implement workaround for errata 852427 |