fix(uuid): add missing `#include` directives

These include directives were missing from both `uuid.h` files.

Change-Id: I875dfda3e0985728277b72f0e7597dde5cf9d304
Signed-off-by: Chris Kay <chris.kay

fix(uuid): add missing `#include` directives

These include directives were missing from both `uuid.h` files.

Change-Id: I875dfda3e0985728277b72f0e7597dde5cf9d304
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "feat(hcx): initialize HCRX_EL2 to its default value" into integration

Merge "fix(rpi3): initialize SD card host controller" into integration

fix(rpi3): initialize SD card host controller

Add initial configuration parameters for Rasperry Pi 3's sdhost
controller, and then configure and use those parameters.

This change allows warm reboot

fix(rpi3): initialize SD card host controller

Add initial configuration parameters for Rasperry Pi 3's sdhost
controller, and then configure and use those parameters.

This change allows warm reboots of UEFI on Raspberry Pi 3B+ where
existing code often fails with "unknown error". See discussion at:

https://github.com/pftf/RPi3/issues/24

The basic idea is that some initial configuration parameters
(clock rate, bus width) aren't configured into the hardware before
commands start being sent. I suspect that the particular setting
that matters is the "slow card" bit, but the initial clock setting
also seemed wrong to me.

Change-Id: I526def340def143f23f3422f1fc14c12c937ca7f
Signed-off-by: Rob Newberry <robthedude@mac.com>

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feat(hcx): initialize HCRX_EL2 to its default value

The value of register HCRX_EL2 is UNKNOWN out of reset. This can
affect the behavior in lower exception levels, such as traps to
EL2 due to a wron

feat(hcx): initialize HCRX_EL2 to its default value

The value of register HCRX_EL2 is UNKNOWN out of reset. This can
affect the behavior in lower exception levels, such as traps to
EL2 due to a wrong configuration of the register upon reset.

This patch initializes the register at EL3 and disables all traps
related to it.

On the other hand, new fields have been introduced for HCRX_EL2,
which are now defined in this patch, so they can be used in
further development.

Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: I0bf1e949aa0d3be9f227358ad088a1ecb96ce222

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feat(pie/por): support permission indirection and overlay

Arm v8.9 introduces a series of features providing a new way to set memory
permissions. Instead of directly encoding the permissions in the

feat(pie/por): support permission indirection and overlay

Arm v8.9 introduces a series of features providing a new way to set memory
permissions. Instead of directly encoding the permissions in the page
tables the PTEs contain indexes into an array of permissions stored in
system registers, allowing greater flexibility and density of encoding.

Enable access to these features for EL2 and below, context switching the
newly added EL2 registers as appropriate. Since all of FEAT_S[12]P[IO]E
are separately discoverable we have separate build time options for
enabling them, but note that there is overlap in the registers that they
implement and the enable bit required for lower EL access.

Change the FVP platform to default to handling them as dynamic options so
the right decision can be made by the code at runtime.

Signed-off-by: Mark Brown <broonie@kernel.org>
Change-Id: Icf89e444e39e1af768739668b505661df18fb234

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Merge "style(docs): fix typo s/flase/false/" into integration

feat(cpus): add support for blackhawk cpu

Add basic CPU library code to support the Blackhawk CPU,
BlackHawk core is based out of Hunter ELP core,
so overall library code was adapted based on that.

feat(cpus): add support for blackhawk cpu

Add basic CPU library code to support the Blackhawk CPU,
BlackHawk core is based out of Hunter ELP core,
so overall library code was adapted based on that.

Change-Id: I4750e774732218ee669dceb734cd107f46b78492
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(cpus): add support for chaberton cpu

Add basic CPU library code to support the Chaberton CPU,
Chaberton cores are based out of Hunter core, so overall
library code was adapted based on that.

C

feat(cpus): add support for chaberton cpu

Add basic CPU library code to support the Chaberton CPU,
Chaberton cores are based out of Hunter core, so overall
library code was adapted based on that.

Change-Id: I58321c77f2c364225a764da6fa65656d1bec33f1
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(ethos-n)!: add protected NPU firmware setup

When the Arm(R) Ethos(TM)-N NPU driver is built with TZMP1 support, the
NPU should use the firmware that has been loaded into the protected
memory by

feat(ethos-n)!: add protected NPU firmware setup

When the Arm(R) Ethos(TM)-N NPU driver is built with TZMP1 support, the
NPU should use the firmware that has been loaded into the protected
memory by BL2. The Linux Kernel NPU driver in the non-secure world is
not allowed to configure the NPU to do this in a TZMP1 build so the SiP
service will now configure the NPU to boot with the firmware in the
protected memory.

BREAKING CHANGE: The Linux Kernel NPU driver can no longer directly
configure and boot the NPU in a TZMP1 build. The API version has
therefore been given a major version bump with this change.

Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I65d00f54b3ade3665d7941e270da7a3dec02281a

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feat(ethos-n): add stream extends and attr support

The SiP service for the Arm(R) Ethos(TM)-N NPU driver will now handle
setting up the address extension and attribute control for the NPU's
streams.

feat(ethos-n): add stream extends and attr support

The SiP service for the Arm(R) Ethos(TM)-N NPU driver will now handle
setting up the address extension and attribute control for the NPU's
streams. The non-secure world will still be allowed to read the address
extension for stream0 but non-secure access to all other streams have
been removed.

The API version has been given a minor bump with this change to indicate
the added functionality.

Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I2b041ca4a0a2b5cd6344a4ae144f75e137c72592

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feat(ethos-n): add reserved memory address support

The FCONF parsing of the HW_CONFIG for the Arm(R) Ethos(TM)-N NPU now
supports reading the address of the reserved memory setup for the NPU so
the

feat(ethos-n): add reserved memory address support

The FCONF parsing of the HW_CONFIG for the Arm(R) Ethos(TM)-N NPU now
supports reading the address of the reserved memory setup for the NPU so
the address can be used in the SiP service for the NPU.

Change-Id: I0968255a966e84896b00ea935d6aa3d5232c5f7b
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>

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feat(ethos-n): add event and aux control support

The SiP service for the Arm(R) Ethos(TM)-N NPU driver will now handle
setting up the NPU's event and aux control registers during the SMC
reset call.

feat(ethos-n): add event and aux control support

The SiP service for the Arm(R) Ethos(TM)-N NPU driver will now handle
setting up the NPU's event and aux control registers during the SMC
reset call. The aux control register will no longer be accessible by the
non-secure world.

The API version has been given a minor bump with this change to indicate
the added functionality.

Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I5b099e25978aa4089c384eb17c5060c5b4eaf373

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feat(ethos-n): add SMC call to get FW properties

When the Arm(R) Ethos(TM)-N NPU firmware is loaded by BL2 into protected
memory, the Linux kernel NPU driver cannot access the firmware. To still
all

feat(ethos-n): add SMC call to get FW properties

When the Arm(R) Ethos(TM)-N NPU firmware is loaded by BL2 into protected
memory, the Linux kernel NPU driver cannot access the firmware. To still
allow the kernel driver to access some information about the firmware,
SMC calls have been added so it can check compatibility and get the
necessary information to map the firmware into the SMMU for the NPU.

The API version has been given a minor version bump with this change to
indicate the added functionality.

Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: Idb076b7bcf54ed7e8eb39be80114dc1d1c45336d

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feat(ethos-n): add check for NPU in SiP setup

The SiP service in the Arm(R) Ethos(TM)-N NPU driver requires that there
is at least one NPU available. If there is no NPU available, the driver
is eith

feat(ethos-n): add check for NPU in SiP setup

The SiP service in the Arm(R) Ethos(TM)-N NPU driver requires that there
is at least one NPU available. If there is no NPU available, the driver
is either used incorrectly or the HW config is incorrect.

To ensure that the SiP service is not incorrectly used, a setup handler
has been added to the service that will validate that there is at least
one NPU available.

Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I8139a652f265cfc0db4a37464f39f1fb92868e10

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fix(ethos-n): add workaround for erratum 2838783

To workaround Arm(R) Ethos(TM)-N NPU erratum 2838783, the NPU has been
configured to allow being woken up by both secure and non-secure events
to mak

fix(ethos-n): add workaround for erratum 2838783

To workaround Arm(R) Ethos(TM)-N NPU erratum 2838783, the NPU has been
configured to allow being woken up by both secure and non-secure events
to make sure that an event always wakes up the NPU.

The API version has been given a minor version bump with this change to
indicate that this fix is included.

Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I429cdd6bf1e633b4dedf2e94af28937dd892a0ba

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feat(ethos-n): add support for NPU to cert_create

Add Juno specific Makefile to the certificate tool build. That
Makefile is included by the certificate tool Makefile to add
information about the au

feat(ethos-n): add support for NPU to cert_create

Add Juno specific Makefile to the certificate tool build. That
Makefile is included by the certificate tool Makefile to add
information about the authentication data for the
Arm(R) Ethos(TM)-N NPU's firmware binary.

Signed-off-by: Mohamed Elzahhar <Mohamed.Elzahhar@arm.com>
Signed-off-by: Rob Hughes <robert.hughes@arm.com>
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: Ie4b6a1c29d73b3ed5041b57f2cd88033be18a63a

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feat(ethos-n): add NPU support in fiptool

Add platform specific Makefile to add UUIDs and command options
for the Arm(R) Ethos(TM)-N NPU firmware binary and certificate
data to the FIP so that the T

feat(ethos-n): add NPU support in fiptool

Add platform specific Makefile to add UUIDs and command options
for the Arm(R) Ethos(TM)-N NPU firmware binary and certificate
data to the FIP so that the TF-A's BL2 can later be used to load
the Arm(R) Ethos(TM)-N NPU firmware binary into memory and verify
its integrity.

Add separate driver specific include header file for the
Arm(R) Ethos(TM)-N NPU images containing UUIDs and command options
to make it easy to port the FIP support to other platforms.

Signed-off-by: Daniele Castro <daniele.castro@arm.com>
Signed-off-by: Rob Hughes <robert.hughes@arm.com>
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I8cd64fb20d58f8bd539facb085606213d6cead05

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feat(ethos-n): add NPU sleeping SMC call

The non-secure world delegation of the register needed to determine if
the Arm(R) Ethos(TM)-N NPU is active or sleeping will be removed in the
future. In pre

feat(ethos-n): add NPU sleeping SMC call

The non-secure world delegation of the register needed to determine if
the Arm(R) Ethos(TM)-N NPU is active or sleeping will be removed in the
future. In preparation for the change, a new SMC call has been added to
allow the non-secure world to ask the SiP service for the state instead.

A minor API version bump has been done with this change to indicate
support for the new functionality.

Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I1338341be385cf1891f4809efb7083fae6d928bc

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feat(ethos-n): add reset type to reset SMC calls

Adds a reset type argument for the soft and hard reset SMC calls to
indicate whether to perform a full reset and setup or only halt the
Arm(R) Ethos(

feat(ethos-n): add reset type to reset SMC calls

Adds a reset type argument for the soft and hard reset SMC calls to
indicate whether to perform a full reset and setup or only halt the
Arm(R) Ethos(TM)-N NPU. For use in cases where the NPU will not be
used but must be put into a known state, such as suspending the NPU
as part of power management.

Signed-off-by: Joshua Pimm <joshua.pimm@arm.com>
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I6018af85a28b0e977166ec29d26f04739123140c

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fix(aarch64): allow build with ARM_ARCH_MINOR=4

When building the FVP platform with SPMD (which activates the context
switch code), but keeping ARM_ARCH_MINOR to 4 or lower, the assembler
will compl

fix(aarch64): allow build with ARM_ARCH_MINOR=4

When building the FVP platform with SPMD (which activates the context
switch code), but keeping ARM_ARCH_MINOR to 4 or lower, the assembler
will complain about the SCXTNUM_EL2 system register not being supported
by the "selected processor".

Allow building this combination of options by defining the SCXTNUM_EL2
register via the generic S3_ encoding, so any assembler, with any -march
settings, will generate the access without any warnings.

We do protect accesses to this register by runtime checks, if not
explicitly requested otherwise, so can override the toolchain in this
case.

Change-Id: I0941f4c4dcf541bd968c153b9c3fac61ca23f7ef
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(cpufeat): enable FEAT_SVE for FEAT_STATE_CHECKED

Add support for runtime detection (ENABLE_SVE_FOR_NS=2), by splitting
sve_supported() into an ID register reading function and a
second function

feat(cpufeat): enable FEAT_SVE for FEAT_STATE_CHECKED

Add support for runtime detection (ENABLE_SVE_FOR_NS=2), by splitting
sve_supported() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we do SVE specific setup.

Change the FVP platform default to the now supported dynamic
option (=2), so the right decision can be made by the code at runtime.

Change-Id: I1caaba2216e8e2a651452254944a003607503216
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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feat(cpufeat): enable FEAT_SME for FEAT_STATE_CHECKED

Add support for runtime detection (ENABLE_SME_FOR_NS=2), by splitting
feat_sme_supported() into an ID register reading function and a
second fun

feat(cpufeat): enable FEAT_SME for FEAT_STATE_CHECKED

Add support for runtime detection (ENABLE_SME_FOR_NS=2), by splitting
feat_sme_supported() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we do SME specific setup.

Change the FVP platform default to the now supported dynamic option
(=2),so the right decision can be made by the code at runtime.

Change-Id: Ida9ccf737db5be20865b84f42b1f9587be0626ab
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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Merge changes from topic "psci-osi" into integration

* changes:
feat(sc7280): add support for PSCI_OS_INIT_MODE
feat(fvp): enable support for PSCI OS-initiated mode
feat(psci): update PSCI_FEA

Merge changes from topic "psci-osi" into integration

* changes:
feat(sc7280): add support for PSCI_OS_INIT_MODE
feat(fvp): enable support for PSCI OS-initiated mode
feat(psci): update PSCI_FEATURES
feat(psci): add support for OS-initiated mode
feat(psci): add support for PSCI_SET_SUSPEND_MODE
build(psci): add build option for OS-initiated mode
docs(psci): add design proposal for OS-initiated mode

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refactor(amu): use new AMU feature check routines

The AMU extension code was using its own feature detection routines.
Replace them with the generic CPU feature handlers (defined in
arch_features.h)

refactor(amu): use new AMU feature check routines

The AMU extension code was using its own feature detection routines.
Replace them with the generic CPU feature handlers (defined in
arch_features.h), which get updated to cover the v1p1 variant as well.

Change-Id: I8540f1e745d7b02a25a6c6cdf2a39d6f5e21f2aa
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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