| 0b850e9e | 22-Apr-2023 |
Raghu Krishnamurthy <raghu.ncstate@gmail.com> |
feat(spmd): add partition info get regs
This patch adds support for an EL3 SPMD logical partition to discover
secure partitions using the FFA_PARTITION_INFO_GET_REGS abi. It also
adds helper functio
feat(spmd): add partition info get regs
This patch adds support for an EL3 SPMD logical partition to discover
secure partitions using the FFA_PARTITION_INFO_GET_REGS abi. It also
adds helper functions for a logical partition to use the information
returned in registers in a meaningful way.
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: Id69488e7367e17e2dfa6c8e332be3c8d41f6c773
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|
| 5ca1619f | 22-Apr-2023 |
Raghu Krishnamurthy <raghu.ncstate@gmail.com> |
refactor(ff-a): move structure definitions
Move ffa_partition_info_get definitions from EL3 SPMC private header
files to common header files. The structures are common to FF-A and are
useful for the
refactor(ff-a): move structure definitions
Move ffa_partition_info_get definitions from EL3 SPMC private header
files to common header files. The structures are common to FF-A and are
useful for the EL3 SPMD logical partitions.
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: I19de3f6cb3351afa873022da1397a475a84e3d8b
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|
| 66bdfd6e | 03-Mar-2023 |
Raghu Krishnamurthy <raghu.ncstate@gmail.com> |
feat(spmd): el3 direct message API
This patch implements an API that is exposed to SPMD logical partitions
that can be used to send direct messages to a secure partition.
It also adds required code
feat(spmd): el3 direct message API
This patch implements an API that is exposed to SPMD logical partitions
that can be used to send direct messages to a secure partition.
It also adds required code in the SPMD smc handler to complete the
direct response appropriately.
Change-Id: I2d0e38415f13ad4fd28f8984d565036b7d3a9e71
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
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|
| 02586e0e | 05-Jul-2023 |
Juan Pablo Conde <juanpablo.conde@arm.com> |
feat(cpus): add support for Gelas CPU
This patch adds the necessary CPU library code to support the Gelas CPU
Change-Id: I13ec4a8bb7055c1ebd0796a4a1378983d930fcb3
Signed-off-by: Juan Pablo Conde <j
feat(cpus): add support for Gelas CPU
This patch adds the necessary CPU library code to support the Gelas CPU
Change-Id: I13ec4a8bb7055c1ebd0796a4a1378983d930fcb3
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
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|
| 72e8f245 | 08-Aug-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "chore: update to use Arm word across TF-A" into integration |
| 995eaa63 | 08-Aug-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge changes from topic "hm/errata-a710" into integration
* changes:
refactor(cpus): convert the Cortex-A710 to use cpu helpers
refactor(cpus): convert Cortex-A710 to use the errata framework
Merge changes from topic "hm/errata-a710" into integration
* changes:
refactor(cpus): convert the Cortex-A710 to use cpu helpers
refactor(cpus): convert Cortex-A710 to use the errata framework
refactor(cpus): reorder Cortex-A710 errata by ascending order
feat(cpus): make revision procedure call optional
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| 4c700c15 | 01-Aug-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
chore: update to use Arm word across TF-A
Align entire TF-A to use Arm in copyright header.
Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244
Signed-off-by: Govindraj Raja <govindraj.raja@arm.co
chore: update to use Arm word across TF-A
Align entire TF-A to use Arm in copyright header.
Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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|
| 4d22b0e5 | 26-Jun-2023 |
Harrison Mutai <harrison.mutai@arm.com> |
feat(cpus): make revision procedure call optional
For runtime errata, we should avoid generating calls to
`cpu_get_rev_var` unless its necessary. Make the path that generates
this call parameterized
feat(cpus): make revision procedure call optional
For runtime errata, we should avoid generating calls to
`cpu_get_rev_var` unless its necessary. Make the path that generates
this call parameterized, and cache the result in a temporary register to
allow future calls that go down the alternate path to retrieve the cache
CPU revision.
Change-Id: I9882ede76568fbd9a7ccd4caa74eff0c66a7b20e
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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|
| 352366ed | 08-May-2023 |
Rajasekaran Kalidoss <rajasekaran.kalidoss@arm.com> |
refactor(ethos-n): move build flags to ethosn_npu.mk
The build flags to enable the Arm(R) Ethos(TM)-N NPU driver are in arm
platform specific make files i.e. plat/arm/common/arm_common.mk. These
fla
refactor(ethos-n): move build flags to ethosn_npu.mk
The build flags to enable the Arm(R) Ethos(TM)-N NPU driver are in arm
platform specific make files i.e. plat/arm/common/arm_common.mk. These
flags are renamed and moved to ethosn_npu.mk. Other source and make
files are changed to reflect the changes in these flags.
Signed-off-by: Rajasekaran Kalidoss <rajasekaran.kalidoss@arm.com>
Change-Id: I6fd20225343c574cb5ac1f0f32ff2fc28ef37ea6
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|
| 29ae73e3 | 07-Aug-2023 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "mb/mb-signer-id" into integration
* changes:
feat(qemu): add dummy plat_mboot_measure_key() function
docs(rss): update RSS doc for signer-ID
feat(imx): add dummy 'pla
Merge changes from topic "mb/mb-signer-id" into integration
* changes:
feat(qemu): add dummy plat_mboot_measure_key() function
docs(rss): update RSS doc for signer-ID
feat(imx): add dummy 'plat_mboot_measure_key' function
feat(tc): implement platform function to measure and publish Public Key
feat(auth): measure and publicise the Public Key
feat(fvp): implement platform function to measure and publish Public Key
feat(fvp): add public key-OID information in RSS metadata structure
feat(auth): add explicit entries for key OIDs
feat(rss): set the signer-ID in the RSS metadata
feat(auth): create a zero-OID for Subject Public Key
docs: add details about plat_mboot_measure_key function
feat(measured-boot): introduce platform function to measure and publish Public Key
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|
| db8621a2 | 04-Aug-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge changes from topic "ar/errata_refactor" into integration
* changes:
fix(cpus): workaround for Neoverse N2 erratum 2779511
fix(errata-abi): added Neoverse N2 to Errata ABI list
fix(cpus):
Merge changes from topic "ar/errata_refactor" into integration
* changes:
fix(cpus): workaround for Neoverse N2 erratum 2779511
fix(errata-abi): added Neoverse N2 to Errata ABI list
fix(cpus): workaround for Neoverse N2 erratum 2743014
fix(docs): updated certain Neoverse N2 erratum status in docs
refactor(cpus): convert Neoverse N2 to use CPU helpers
refactor(cpus): convert Neoverse N2 to framework
refactor(cpus): reorder Neoverse N2 errata by ascending order
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|
| f6af2185 | 21-Jul-2023 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
refactor(cpus): convert Neoverse V1 to use CPU helpers
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Idb4b47982278cda93a7c0f0a49dfceb75b8d88e4 |
| 12d28067 | 17-Jul-2023 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
fix(cpus): workaround for Neoverse N2 erratum 2779511
Neoverse N2 erratum 2779511 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set bit[47] of CP
fix(cpus): workaround for Neoverse N2 erratum 2779511
Neoverse N2 erratum 2779511 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set bit[47] of CPUACTLR3_EL1
SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Iaa0e30de8473ecb1df1fcca3a45904aac2e419b3
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|
| eb44035c | 05-Jul-2023 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
fix(cpus): workaround for Neoverse N2 erratum 2743014
Neoverse N2 erratum 2743014 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set CPUACTLR5_EL1
fix(cpus): workaround for Neoverse N2 erratum 2743014
Neoverse N2 erratum 2743014 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ie7e1be5dea9d1f74738f9fed0fb58bfd41763192
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|
| 6fb2dbd2 | 15-Jun-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
refactor(cpus): convert the Cortex-A76 to use the errata framework
Testing:
- Manual comparison of disassembly with and without conversion.
- Using the test script in gerrit - 19136
- Build
refactor(cpus): convert the Cortex-A76 to use the errata framework
Testing:
- Manual comparison of disassembly with and without conversion.
- Using the test script in gerrit - 19136
- Building with errata and stepping through from ArmDS and running tftf.
Change-Id: I126f09de44b16e8bbb7e32477b880b4650eef23b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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|
| 890b5088 | 25-Feb-2023 |
Raghu Krishnamurthy <raghu.ncstate@gmail.com> |
feat(spmd): add spmd logical partitions
Add header file to help with creation of SPMD logical partitions. Also
update linker files to create sections to record SPMD logical partitions
declared. This
feat(spmd): add spmd logical partitions
Add header file to help with creation of SPMD logical partitions. Also
update linker files to create sections to record SPMD logical partitions
declared. This follows the same pattern as the EL3 SPMC's logical
partitions. This patch also adds initialization of SPMD logical
partitions when the SPMD comes up.
ENABLE_SPMD_LP is a build flag that is used to enable support for
SPMD logical partitions.
Note that the approach chosen is to keep SPMD and SPMC logical
partition support separate, as opposed to extend the existing SPMC
logical partition support since the code would need to have a number of
ifdefs and the interactions with various build options such as
SPMC_AT_EL3 needs to be accounted for, which would make code more
complicated.
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: I9642ddbf6ea26dd3f4a283baec598d61c07e3661
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|
| 4a530b4c | 10-Jul-2023 |
Juan Pablo Conde <juanpablo.conde@arm.com> |
feat(cpufeat): initialize HFG*_EL2 registers
HFG*_EL2 registers control the fine-grained traps introduced by
FEAT_FGT. These traps come enabled by default so old systems unaware
of this feature can
feat(cpufeat): initialize HFG*_EL2 registers
HFG*_EL2 registers control the fine-grained traps introduced by
FEAT_FGT. These traps come enabled by default so old systems unaware
of this feature can be trapped to EL3, not being able to handle the
trap correctly. This patch disables all fine-grained traps by default
to prevent such unexpected behavior.
Change-Id: If2ae97accbeed2bea51ae03b5225ce762ecffb25
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
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|
| f1e4a28d | 21-Jul-2023 |
Omkar Anand Kulkarni <omkar.kulkarni@arm.com> |
feat(arm): enable FHI PPI interrupt to report CPU errors
To handle the core corrected errors in the firmware, the FHI PPI
interrupt has to be enabled on all the cores. At boot, when the RAS
framewor
feat(arm): enable FHI PPI interrupt to report CPU errors
To handle the core corrected errors in the firmware, the FHI PPI
interrupt has to be enabled on all the cores. At boot, when the RAS
framework is initialized, only primary core is up and hence core FHI PPI
interrupt is enabled only on primary core. This patch adds support to
configure and enable core FHI interrupt for all the secondary cores as
part of their boot sequence.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I4b25152cb498fe975b9c770babb25aa9e01f9656
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|
| b74a1938 | 31-Jul-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(nuvoton): added support for npcm845x chip" into integration |
| 0cffcdd6 | 19-Jul-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(auth): add explicit entries for key OIDs
Key-OIDs that authenticate BL31, BL31(SOC)-FW config, and HW config
images have been explicitly entered.
Implementations of signer-ID consume these entr
feat(auth): add explicit entries for key OIDs
Key-OIDs that authenticate BL31, BL31(SOC)-FW config, and HW config
images have been explicitly entered.
Implementations of signer-ID consume these entries.
Change-Id: I24c9085ed5f266af06d40fb73302e35d857a9d5b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| 60861a04 | 11-Apr-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(rss): set the signer-ID in the RSS metadata
Calculate a hash of the public key and put that into the signer-ID
field of the relevant RSS metadata. The signer-ID metadata is mandatory
in the Arm
feat(rss): set the signer-ID in the RSS metadata
Calculate a hash of the public key and put that into the signer-ID
field of the relevant RSS metadata. The signer-ID metadata is mandatory
in the Arm CCA attestation scheme.
Change-Id: Ic846d8bf882cfea8581d3523a3461c919462df30
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| 9505d03e | 11-Apr-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(auth): create a zero-OID for Subject Public Key
Created an explicit zero-OID which can be used for Subject
Public Key that do not have their own key identifier.
With this, all keys (including
feat(auth): create a zero-OID for Subject Public Key
Created an explicit zero-OID which can be used for Subject
Public Key that do not have their own key identifier.
With this, all keys (including the subject public key) have
a proper key OID string so we don't need to make a special
case of null pointers when it comes to handling key OIDs.
Change-Id: Ice6923951699b6e253d7fd87e4c1b912470e0391
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| a29cb3c0 | 11-Apr-2023 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
refactor(cpus): convert the Cortex-A510 to use cpu helpers
Change-Id: I6d26092525c2d5255a741515071ee7ed873aa52d
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
| 445f7b51 | 19-Jun-2023 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
feat(cpus): add errata framework helpers
Adding an helper macro for bit field insert(bic) instruction
to group all the operations related to it.
Change-Id: Idfd06c7f38faf52090f62b458d2d96c2682f63fe
feat(cpus): add errata framework helpers
Adding an helper macro for bit field insert(bic) instruction
to group all the operations related to it.
Change-Id: Idfd06c7f38faf52090f62b458d2d96c2682f63fe
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
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|
| edcece15 | 19-Mar-2023 |
rutigl@gmail.com <rutigl@gmail.com> |
feat(nuvoton): added support for npcm845x chip
Initial version
Signed-off-by: Margarita Glushkin <rutigl@gmail.com>
Change-Id: If433d325a90b519ae5f02411865bffd368ff2824 |