fix(cpus): workaround for C1-Premium erratum 3865171

C1-Premium erratum 3865171 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUA

fix(cpus): workaround for C1-Premium erratum 3865171

C1-Premium erratum 3865171 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR2_EL1[22] to 1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/111078/latest

Change-Id: I0b97dfc1dd989e4d3e35716b0163b99c9719a0e6
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Premium erratum 3815514

C1-Premium erratum 3815514 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUA

fix(cpus): workaround for C1-Premium erratum 3815514

C1-Premium erratum 3815514 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR5[13] to 1.
This is expected to result in a small performance degradation
for workloads that use MTE. The degradation might be
approximately 1.6% when using MTE imprecise mode or 0.9% for
MTE precise mode.

SDEN documentation:
https://developer.arm.com/documentation/111078/latest

Change-Id: Id52a1a077459bd16de16b1ae00fc783250d197ed
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Premium erratum 3684152

C1-Premium erratum 3684152 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by setting CPUA

fix(cpus): workaround for C1-Premium erratum 3684152

C1-Premium erratum 3684152 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR_EL1[60:58] to
3'b001, which has a small performance impact.

SDEN documentation:
https://developer.arm.com/documentation/111078/latest

Change-Id: I2e677b0e6cf3ce453eae54300c5c0072d734a341
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Premium erratum 3502731

C1-Premium erratum 3502731 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by setting CPUA

fix(cpus): workaround for C1-Premium erratum 3502731

C1-Premium erratum 3502731 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR4[23] to 1,
which will disable Memory Renaming optimization.
The performance impact of setting this chicken bit is about
0.82% in GB6.

SDEN documentation:
https://developer.arm.com/documentation/111078/latest

Change-Id: Idc6ec2a742ed0f974d026aa63d7c9c5b248ef33b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge changes from topic "xl/c1ultra-errata" into integration

* changes:
fix(cpus): workaround for C1-Ultra erratum 3324333
fix(cpus): workaround for C1-Ultra erratum 3658374
fix(cpus): workar

Merge changes from topic "xl/c1ultra-errata" into integration

* changes:
fix(cpus): workaround for C1-Ultra erratum 3324333
fix(cpus): workaround for C1-Ultra erratum 3658374
fix(cpus): workaround for C1-Ultra erratum 3926381
fix(cpus): workaround for C1-Ultra erratum 4102704
fix(cpus): workaround for C1-Ultra erratum 3865171
fix(cpus): workaround for C1-Ultra erratum 3815514
fix(cpus): workaround for C1-Ultra erratum 3705939
fix(cpus): workaround for C1-Ultra erratum 3684152
fix(cpus): workaround for C1-Ultra erratum 3651221
fix(cpus): workaround for C1-Ultra erratum 3502731

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fix(cpus): workaround for C1-Ultra erratum 3658374

C1-Ultra erratum 3658374 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

This is workaround for accessing ICH_VMCR_EL2.

fix(cpus): workaround for C1-Ultra erratum 3658374

C1-Ultra erratum 3658374 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

This is workaround for accessing ICH_VMCR_EL2.
When ICH_VMCR_EL2.VBPR1 is written in Secure state (SCR_EL3.NS==0)
and then subsequently read in Non-secure state (SCR_EL3.NS==1), a
wrong value might be returned. The same issue exists in the opposite way.

Adding workaround in EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored. For example, EL3 software should set
SCR_EL3.NS to 1 when saving or restoring the value ICH_VMCR_EL2 for
Non-secure(or Realm) state. EL3 software should clear
SCR_EL3.NS to 0 when saving or restoring the value ICH_VMCR_EL2 for
Secure state.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I945477b2432fefc04049e8576b66cea0cbffb03a
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Ultra erratum 3926381

C1-Ultra erratum 3926381 is a Cat B erratum that applies
to revision r1p0 and is open.

This errata can be avoided by executing an implementation
s

fix(cpus): workaround for C1-Ultra erratum 3926381

C1-Ultra erratum 3926381 is a Cat B erratum that applies
to revision r1p0 and is open.

This errata can be avoided by executing an implementation
specific instruction patching sequence as soon as possible
after boot. After it is applied, the code only converts
WFx and WFxT instructions to NOP when PSTATE.SM=1 or when
PSTATE.ZA=1.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I2e0f3a715670aaac116c7d3c5f5992ff7ab05ba3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Ultra erratum 3865171

C1-Ultra erratum 3865171 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for C1-Ultra erratum 3865171

C1-Ultra erratum 3865171 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR2_EL1[22] to 1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I8bfe15fdd1d028d43d8730e7d43f72c9f15810d7
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for C1-Ultra erratum 3815514

C1-Ultra erratum 3815514 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for C1-Ultra erratum 3815514

C1-Ultra erratum 3815514 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR5_EL1[13] to 1.
Setting CPUACTLR5_EL1[13] to 1 is expected to result in a small
performance degradation for workloads that use MTE. The
degradation might be approximately 1.6% when using MTE imprecise
mode or 0.9% for MTE precise mode.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I2d6b0ee282010139d8dc406800f2738b39113957
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for C1-Ultra erratum 3684152

C1-Ultra erratum 3684152 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR_EL

fix(cpus): workaround for C1-Ultra erratum 3684152

C1-Ultra erratum 3684152 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR_EL1[60:58] to
3'b001, which has a small perf impact.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I3747b2a99785602bd2a3bddac3a69a934e7f4b37
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for C1-Ultra erratum 3502731

C1-Ultra erratum 3502731 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for C1-Ultra erratum 3502731

C1-Ultra erratum 3502731 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR4[23] to 1,
which will disable Memory Renaming optimization.
The performance impact of setting this chicken bit is about
0.82% in GB6.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: Iaf832b66aeed937edbb1e9be29de41b0f2b5d70c
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(rse): remove host ROTPK support and test

Remove support for the retrieving a host ROTPK from the RSE, as the RSE
no longer has host ROTPKs provisioned by default. Also remove the TC
test which v

fix(rse): remove host ROTPK support and test

Remove support for the retrieving a host ROTPK from the RSE, as the RSE
no longer has host ROTPKs provisioned by default. Also remove the TC
test which verified this feature.

BREAKING CHANGE: platforms can no longer retrieve the host ROTPK from
the RSE as these are no longer provisioned.

Change-Id: I2c852855e53c36e77f639f17f4c181290d95ccff
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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Merge "feat(cpufeat): enable USE_SPINLOCK_CAS to FEAT_STATE_CHECKED" into integration

feat(cpufeat): enable USE_SPINLOCK_CAS to FEAT_STATE_CHECKED

The FEAT_LSE enablement predates the FEAT_STATE framework and has never
been converted. Since the introduction of USE_SPINLOCK_CAS we've

feat(cpufeat): enable USE_SPINLOCK_CAS to FEAT_STATE_CHECKED

The FEAT_LSE enablement predates the FEAT_STATE framework and has never
been converted. Since the introduction of USE_SPINLOCK_CAS we've gained
lots of quality of life features that allow for better feature
enablement. This patch converts USE_SPINLOCK_CAS to tri-state and adds
it to FEATURE_DETECTION to align with all other features.

Instead of introducing the assembly checking for tri-state, this patch
translates all locking routines to C inline assembly and uses the
standard C helpers. The main benefit is that this gives greater
visibility to the compiler about what the functions are doing and lets
it optimise better. Namely, it is able to allocate registers itself and
inline the functions when LTO is enabled.

An unsuccessful attempt was made to use the instructions directly and
have even flow control in C. This, however, made code very complicated
and less efficient in the tight loops of the spinlock.

The last use of ARM_ARCH_AT_LEAST goes away with this change and so this
macro is removed. It has now been fully superseded by the FEAT_STATE
framework.

This change exposes a limitation - RME_GPT_BITLOCK_BLOCK requires
USE_SPINLOCK_CAS. This patch does not address this in any way but makes
the relationship explicit.

Change-Id: I580081549aceded2dca3e0f4564ee7510a7e56ae
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(cpufeat): always provide pauth context helper

We need to be able to work on the structure with or without pauth.
Arrange the getter so that it can compile even if it wouldn't be
functional.

Cha

fix(cpufeat): always provide pauth context helper

We need to be able to work on the structure with or without pauth.
Arrange the getter so that it can compile even if it wouldn't be
functional.

Change-Id: I563680fc76f4e08d3e77e01ed7525d09c7c617ab
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(cm): remove set_aapcs_args functions" into integration

fix(cm): remove set_aapcs_args functions

These functions were added as wrappers on context but were never used,
mainly because we sometimes only have a reference to the gpregs
sub-struct. Remove the

fix(cm): remove set_aapcs_args functions

These functions were added as wrappers on context but were never used,
mainly because we sometimes only have a reference to the gpregs
sub-struct. Remove them to reduce clutter.

Change-Id: If10dade6ea9cc90384344cf0149482574cf0e116
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(security): add CVE-2024-7881 mitigation to C1-Ultra CPU

This patch mitigates Cat B erratum 3651221 [2] / CVE-2024-7881 [1]
for C1-Ultra CPU. This CVE applies to r0p0 and is fixed in r1p0 [2].

T

fix(security): add CVE-2024-7881 mitigation to C1-Ultra CPU

This patch mitigates Cat B erratum 3651221 [2] / CVE-2024-7881 [1]
for C1-Ultra CPU. This CVE applies to r0p0 and is fixed in r1p0 [2].

This CVE can be mitigated by disabling the affected prefetcher
setting CPUACTLR6_EL1[41].

[1] https://developer.arm.com/documentation/110326/latest/
[2] https://developer.arm.com/documentation/111077/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I7815d6fc9af812c38b1c05881c850b8209d6ad7c

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fix(security): add CVE-2024-7881 mitigation to C1-Premium CPU

This patch mitigates Cat B erratum 3651221 [2] / CVE-2024-7881 [1]
for C1-Premium CPU. This CVE applies to r0p0 and
is fixed in r1p0 [2]

fix(security): add CVE-2024-7881 mitigation to C1-Premium CPU

This patch mitigates Cat B erratum 3651221 [2] / CVE-2024-7881 [1]
for C1-Premium CPU. This CVE applies to r0p0 and
is fixed in r1p0 [2].

This CVE can be mitigated by disabling the affected prefetcher
setting CPUACTLR6_EL1[41].

[1] https://developer.arm.com/documentation/110326/latest/
[2] https://developer.arm.com/documentation/111078/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I70b50700bc1618e0f8f4121efc9fe89e2742ed74

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Merge changes from topic "xl/a725-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A725 erratum 3456106
fix(cpus): workaround for Cortex-A725 erratum 3711914
fix(cpus): wor

Merge changes from topic "xl/a725-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A725 erratum 3456106
fix(cpus): workaround for Cortex-A725 erratum 3711914
fix(cpus): workaround for Cortex-A725 erratum 2936490
fix(cpus): workaround for Cortex-A725 erratum 2874943

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fix(cpus): workaround for Cortex-A725 erratum 3711914

Cortex-A725 erratum 3711914 is a Cat B erratum that applies
to revisions r0p0 and r0p1 and it is fixed in r0p2.

This erratum can be avoided by

fix(cpus): workaround for Cortex-A725 erratum 3711914

Cortex-A725 erratum 3711914 is a Cat B erratum that applies
to revisions r0p0 and r0p1 and it is fixed in r0p2.

This erratum can be avoided by inserting a DMB LD after each DSB ST instruction.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest/

Change-Id: If3b9d3a0f495b3a172d3e6e5ca7afa8c30aeb4ea
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A725 erratum 2936490

Cortex-A725 erratum 2936490 is a Cat B erratum that applies
to revisions in r0p0, and is fixed in r0p1.

This erratum can be avoided by setting

fix(cpus): workaround for Cortex-A725 erratum 2936490

Cortex-A725 erratum 2936490 is a Cat B erratum that applies
to revisions in r0p0, and is fixed in r0p1.

This erratum can be avoided by setting CPUACTLR2_EL1[37] to 1.
Setting this bit is expected to have a negligible performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest/

Change-Id: I9833f8831ba3735a94763791a65be11b95c00bdb
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A725 erratum 2874943

Cortex-A725 erratum 2874943 is a Cat B erratum that applies
to revision r0p0 when FEAT_SPE is enabled, it is fixed in r0p1.

This erratum can be

fix(cpus): workaround for Cortex-A725 erratum 2874943

Cortex-A725 erratum 2874943 is a Cat B erratum that applies
to revision r0p0 when FEAT_SPE is enabled, it is fixed in r0p1.

This erratum can be avoided by setting bits[58:57] to 0b11 in CPUACTLR_EL1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest/

Change-Id: I686bbde8756d52afee92097ec05b97138b550025
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 1969401

Cortex-A76AE erratum 1969401 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by inserting a

fix(cpus): workaround for Cortex-A76AE erratum 1969401

Cortex-A76AE erratum 1969401 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by inserting a DMB ST before acquire
atomic instructions without release semantics.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: I893452450d430833e6c5a8e33a1e37b708218576
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 1931435

Cortex-A76AE erratum 1931435 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPU

fix(cpus): workaround for Cortex-A76AE erratum 1931435

Cortex-A76AE erratum 1931435 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPUACTLR_EL1[13] to 1. This bit
delays instruction fetch after branch misprediction. This workaround
will have a small impact on performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: I1baba8752f5f2e2ab5c873030e1f00cbb8cf1e60
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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