chore(libfdt): update libfdt to v1.7.2

Where previously we cherry-picked individual sources from the libfdt
project tree, this change instead integrates the entire project tree
into the TF-A reposit

chore(libfdt): update libfdt to v1.7.2

Where previously we cherry-picked individual sources from the libfdt
project tree, this change instead integrates the entire project tree
into the TF-A repository. Doing so reduces the manual overhead of
updating libfdt in the future, as we avoid the need to analyse
individual source-level dependencies.

libfdt, conveniently, also provides a Makefile designed to ease its
integration into foreign build systems (like TF-A's), which we also make
use of in this change.

Source: https://git.kernel.org/pub/scm/utils/dtc/dtc.git/tree/?h=v1.7.2
Change-Id: I8babcfd27019fdd6d255d550491e1bb733745f27
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge changes from topic "bk/simpler_panic" into integration

* changes:
fix(aarch64): do not print EL1 registers on EL3 panic
refactor(el3-runtime): streamline cpu_data assembly offsets using th

Merge changes from topic "bk/simpler_panic" into integration

* changes:
fix(aarch64): do not print EL1 registers on EL3 panic
refactor(el3-runtime): streamline cpu_data assembly offsets using the cpu_ops template

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feat(cpus): add support for Dionysus cpu library

Add basic CPU library code to support the Dionysus CPU.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I4e6b3c7e7369b7cbf0

feat(cpus): add support for Dionysus cpu library

Add basic CPU library code to support the Dionysus CPU.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I4e6b3c7e7369b7cbf0e18d295e5ef5352f621e44

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fix(libfdt): add suffix 'U' to unsigned integers

This corrects the MISRA violation C2012-7.2:
A “u” or “U” suffix shall be applied to all integer constants that
are represented in an unsigned type.

fix(libfdt): add suffix 'U' to unsigned integers

This corrects the MISRA violation C2012-7.2:
A “u” or “U” suffix shall be applied to all integer constants that
are represented in an unsigned type.
Suffix "U" is added to unsigned integers to fix this violation.

Change-Id: I440a51d944c8772b32c1a80783d19ebcdc87221e
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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Merge changes from topic "gr/cpu_lib" into integration

* changes:
feat(cpus): add support for caddo cpu
feat(cpus): add support for veymont cpu

Merge changes from topic "gr/spectre_bhb_updates" into integration

* changes:
fix(security): fix Neoverse V2 CVE-2022-23960
fix(security): fix Cortex-X3 CVE-2022-23960
fix(security): fix Corte

Merge changes from topic "gr/spectre_bhb_updates" into integration

* changes:
fix(security): fix Neoverse V2 CVE-2022-23960
fix(security): fix Cortex-X3 CVE-2022-23960
fix(security): fix Cortex-A715 CVE-2022-23960
fix(security): fix spectre bhb loop count for Cortex-A720

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Merge "fix(cm): deprecate use of NS_TIMER_SWITCH" into integration

feat(cpus): add support for caddo cpu

Add basic CPU library code to support Caddo CPU

Change-Id: I4b431771ebe6f23eb02f3301ff656cfcd4956f81
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

feat(cpus): add support for veymont cpu

Add basic CPU library code to support Veymont CPU

Change-Id: I44db5650e7c9cf8fcc368c935574f4702c373dae
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

fix(cpus): workaround for Cortex-A720 erratum 3711910

Cortex-A720 erratum 3711910 is a Cat B erratum that applies to
revisions r0p0, r0p1 and r0p2, and is still open.

SDEN documentation:
https://de

fix(cpus): workaround for Cortex-A720 erratum 3711910

Cortex-A720 erratum 3711910 is a Cat B erratum that applies to
revisions r0p0, r0p1 and r0p2, and is still open.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2439421

Change-Id: Id65d5ba41b96648b07c09df77fb25cc4bdb50800
Signed-off-by: John Powell <john.powell@arm.com>

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Merge "fix(cm): remove unused macro" into integration

Merge "fix(lib): align round_up with MISRA 10.1 and 10.8" into integration

Merge changes from topic "ar/v2_errata" into integration

* changes:
fix(cpus): workaround for Neoverse-V2 erratum 3701771
fix(cpus): workaround for Neoverse-V2 erratum 3841324

Merge "fix: remove unused cpu_data related macros" into integration

fix(cpus): workaround for Neoverse-V2 erratum 3701771

Neoverse-V2 erratum 3701771 that applies to r0p0, r0p1, r0p2 is
still Open.

The workaround is for EL3 software that performs context save/resto

fix(cpus): workaround for Neoverse-V2 erratum 3701771

Neoverse-V2 erratum 3701771 that applies to r0p0, r0p1, r0p2 is
still Open.

The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.

The mitigation is implemented in commit 7455cd172 and this patch should be applied on top of it.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ic0ad68f7bd393bdc03343d5ba815adb23bf6a24d

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fix(security): fix spectre bhb loop count for Cortex-A720

fix@c2a15217c3053117f4d39233002cb1830fa96670
based on https://developer.arm.com/documentation/110280/latest/
Spectre-BHB loop count K value

fix(security): fix spectre bhb loop count for Cortex-A720

fix@c2a15217c3053117f4d39233002cb1830fa96670
based on https://developer.arm.com/documentation/110280/latest/
Spectre-BHB loop count K value for Cortex-A720 is 38.

Change-Id: Ib6862dbed55e5ffcd0fcd58b45a88cf925c54154
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(cpus): workaround for Neoverse-V2 erratum 3841324

Neoverse-V2 erratum 3841324 is a Cat B erratum that applies to
r0p0 and r0p1. It is fixed in r0p2.

This erratum can be avoided by setting CPUAC

fix(cpus): workaround for Neoverse-V2 erratum 3841324

Neoverse-V2 erratum 3841324 is a Cat B erratum that applies to
r0p0 and r0p1. It is fixed in r0p2.

This erratum can be avoided by setting CPUACTLR_EL1[1]
prior to enabling MMU. This bit will disable a branch predictor
power savings feature. Disabling this power feature
results in negligible power movement and no performance impact.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I9b3a5266103e5000d207c7a270c65455d0646102

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Merge "refactor(el3-runtime): move context security states to context.h" into integration

fix(cm): remove unused macro

It is never referenced.

Change-Id: I538b1f3d8660426faf5bafa68ecda2d637b0bc50
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

Merge "refactor(el3-runtime): extract cpu_data limitations to top-level constraints" into integration

feat(cpufeat): enable FEAT_CPA2 for EL3

FEAT_CPA2 enables checked pointer arithmetic, which in the event
of an arithmetic overflow in pointer generation will result in a
non-canonical pointer being

feat(cpufeat): enable FEAT_CPA2 for EL3

FEAT_CPA2 enables checked pointer arithmetic, which in the event
of an arithmetic overflow in pointer generation will result in a
non-canonical pointer being generated and subsequent address fault.

Note that FEAT_CPA is a trivial implementation that exists in
some hardware purely so it can run CPA2-enabled instructions
without crashing but they don't actually have checked arithmetic,
so FEAT_CPA is not explicitly enabled in TF-A.

Change-Id: I6d2ca7a7e4b986bb9e917aa8baf8091a271c168b
Signed-off-by: John Powell <john.powell@arm.com>

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refactor(el3-runtime): streamline cpu_data assembly offsets using the cpu_ops template

The cpu_data structure, just like cpu_ops, is collection of disparate
data that must be accessible from both C

refactor(el3-runtime): streamline cpu_data assembly offsets using the cpu_ops template

The cpu_data structure, just like cpu_ops, is collection of disparate
data that must be accessible from both C and assembly. Achieving this is
tricky as there is no way to export structure offsets from C directly so
they must be manually recreated with `#define`s and asserts. However,
the cpu_data structure is quite old and the assembly offsets are a
patchwork of additions and extremely difficult to reason with and
modify. In fact, certain currently unused builds with
ENABLE_RUNTIME_INSTRUMENTATION=1 fail to build.

To untangle this, convert the assembly offsets to the pattern used for
the cpu_ops structure. That is, first define the sizes of every member,
as generically as possible, and then chain their offsets one after the
other. To make sure this is always correct, add a CASSERT for the offset
of every member. This makes it easy to modify the structure and fixes
the build failures.

Change-Id: I61aeb55e9c494896663a3c719c10e3c072f56349
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix: remove unused cpu_data related macros

There are no uses for CPU_DATA_PSCI_LOCK_OFFSET so it is removed.

PLAT_PCPU_DATA_SIZE is also unused in ST platforms and causes offsets
to mismatch when t

fix: remove unused cpu_data related macros

There are no uses for CPU_DATA_PSCI_LOCK_OFFSET so it is removed.

PLAT_PCPU_DATA_SIZE is also unused in ST platforms and causes offsets
to mismatch when the linker garbage collects it. It is also removed.

CPU_DATA_PLAT_PCPU_OFFSET is also removed as its only use is in
rcar_lock_get() and related macros which are never called since all
calls of these macros lack an argument.

Change-Id: I883ab58c56b4082e0e8b19a8d8f6186945bcc58e
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(el3-runtime): move context security states to context.h

The three security states (S, NS, RL) are architecturally quite
consistent - anything that uses them has the same numerical assignmen

refactor(el3-runtime): move context security states to context.h

The three security states (S, NS, RL) are architecturally quite
consistent - anything that uses them has the same numerical assignments
(0, 1, 2) and they are quite convenient for indexing. However, we're not
as consistent in tf-a and this is defined in a few places. Since
cpu_data has a dependency on the context management library, use its
security state convention in a few more places and take away this
responsibility from cpu_data.

Change-Id: Iec73b2be2eef91975554767557de72424d0031f1
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(el3-runtime): extract cpu_data limitations to top-level constraints

CRASH_REPORTING is checked via an `#error` statement in the header,
while EL3_EXCEPTION_HANDLING is carefully carved out

refactor(el3-runtime): extract cpu_data limitations to top-level constraints

CRASH_REPORTING is checked via an `#error` statement in the header,
while EL3_EXCEPTION_HANDLING is carefully carved out when not supported.
However, both are only used on AArch64 builds and never on AArch32. We
can promote both to proper make constraints and keep the cpu_data
implementation a little bit simpler.

Change-Id: Ia164e046f953a552dc6e6cf624961a90669eaeeb
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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