| ff8767cb | 25-Sep-2020 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
feat(stm32mp1-fdts): add nvmem_layout node and OTP definitions
A new nvmem_layout node includes nvmem platform-dependent layout
information, such as OTP NVMEM cell lists (phandle, name).
This list a
feat(stm32mp1-fdts): add nvmem_layout node and OTP definitions
A new nvmem_layout node includes nvmem platform-dependent layout
information, such as OTP NVMEM cell lists (phandle, name).
This list allows easy access to OTP offsets defined in BSEC node,
where more OTP definitions with offsets in bytes and length have
been added (replace hard-coded values).
Each board may redefine this list, especially for board_id info.
Change-Id: I910ae671b3bf3320ee6500fecc9ec335ae67bbda
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 195381a9 | 14-May-2021 |
Andre Przywara <andre.przywara@arm.com> |
fix(arm_fpga): Change PL011 UART IRQ
About a year ago there was a change in the underlying Arm platform design
framework, which lead to a reorganisation of the interrupt map (to make
room for multi-
fix(arm_fpga): Change PL011 UART IRQ
About a year ago there was a change in the underlying Arm platform design
framework, which lead to a reorganisation of the interrupt map (to make
room for multi-chip designs).
This lead to the PL011 debug UART interrupt to move from SPI 115 to SPI
415. Unfortunately there is not a good or easy way to auto-detect this
change: Flooding the TX FIFO and checking GICD_ISPENDR registers might
be possible, but sounds a bit over the top for BL31.
So we would need to break one group of images: newer ones, as we do right
now, or older ones.
By now every interesting FPGA image seems to use the newer IRQ, so in
the interest of having a smooth experience for most users, lets switch
to this IRQ.
When people are interested in older images, they can either change the
number back in the .dts file, or provide a patched DTB on the FPGA
command line.
Change-Id: I3c7e7b711f5142813bd94eecde3095a4fc555bb3
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| d850169c | 01-Sep-2021 |
Andre Przywara <andre.przywara@arm.com> |
feat(arm_fpga): query PL011 to learn system frequency
The Arm FPGAs run in mostly one clock domain, which is used for the CPU
cores, the generic timer, and also the UART baudrate base clock. This
si
feat(arm_fpga): query PL011 to learn system frequency
The Arm FPGAs run in mostly one clock domain, which is used for the CPU
cores, the generic timer, and also the UART baudrate base clock. This
single clock can have different rates, to compensate for different IP
complexity. So far most images used 10 MHz, but different rates start to
appear.
To avoid patching both the arch timer frequency and UART baud base fixed
clock in the DTB manually, we would like to set the clock rate
automatically. Fortunately the SCP firmware has the actual clock rate
hard coded, and already programs the PL011 UART baud divider register
with the correct value to achieve a 38400 bps baudrate.
So read the two PL011 baudrate divider values and re-calculate the
original base clock from there, to use as the arch timer frequency. If
the arch timer DT node contains a clock-frequency property, we use that
instead, to support overriding and disabling this autodetection.
Change-Id: I9857fbb418deb4644aeb2816f1102796f9bfd3bb
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| cdbbb9f7 | 17-May-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
fix(fdts stm32mp1): update PLL nodes for ED1/EV1 boards
Align STM32MP157C-ED1/EV1 boards PLL nodes with what is done
for DK boards.
Change-Id: I91be408ea1d9b0474caf4965175df33792b7e11e
Signed-off-b
fix(fdts stm32mp1): update PLL nodes for ED1/EV1 boards
Align STM32MP157C-ED1/EV1 boards PLL nodes with what is done
for DK boards.
Change-Id: I91be408ea1d9b0474caf4965175df33792b7e11e
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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| 3e881a88 | 17-May-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
fix(fdts stm32mp1): set ETH clock on PLL4P on ST boards
Set Ethernet source clock on PLL4P. This is required to enable PTP.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ia64fbb
fix(fdts stm32mp1): set ETH clock on PLL4P on ST boards
Set Ethernet source clock on PLL4P. This is required to enable PTP.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ia64fbb681d3f04f2b90f373c5eb044f5daa2836c
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| 4357db5b | 16-Dec-2020 |
Yann Gautier <yann.gautier@st.com> |
feat(fdts stm32mp1): delete nodes for non-used boot devices
Cleanup the BL2 device tree file by removing the nodes for the devices
that are not used to boot, depending on compilation flags.
In SDMMC
feat(fdts stm32mp1): delete nodes for non-used boot devices
Cleanup the BL2 device tree file by removing the nodes for the devices
that are not used to boot, depending on compilation flags.
In SDMMC boot, the gain for the dtb file is about 2.3kB.
Change-Id: I3ba13e06dd22b52cff96f51db2dac94b532c81ae
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 4955d08d | 09-Feb-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
fix(fdts stm32mp1): use 'kHz' as kilohertz abbreviation
The kilohertz unit abbreviation should read 'kHz' in DDR
settings files of stm32mp15.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.
fix(fdts stm32mp1): use 'kHz' as kilohertz abbreviation
The kilohertz unit abbreviation should read 'kHz' in DDR
settings files of stm32mp15.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ifa363094f58dd943ef78c653c3e470a216739b41
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| 8cafbda6 | 25-Feb-2021 |
Nicolas Le Bayon <nicolas.le.bayon@foss.st.com> |
refactor(fdts stm32mp1): move STM32MP DDR node
Move the generic part of DDR node in SOC dtsi file.
DDR dtsi files only include the part configured by CubeMX tool.
Signed-off-by: Patrick Delaunay <p
refactor(fdts stm32mp1): move STM32MP DDR node
Move the generic part of DDR node in SOC dtsi file.
DDR dtsi files only include the part configured by CubeMX tool.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I8c211e9782604da32aeaab98d0ef75fb1cd9c58d
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